hwdev 35 arch/mips/include/asm/mach-pmcs-msp71xx/msp_usb.h u32 hwdev; /* 0xc: Device HW params */ hwdev 8 arch/x86/include/asm/xen/page-coherent.h static inline void *xen_alloc_coherent_pages(struct device *hwdev, size_t size, hwdev 17 arch/x86/include/asm/xen/page-coherent.h static inline void xen_free_coherent_pages(struct device *hwdev, size_t size, hwdev 28 drivers/gpu/drm/arm/malidp_crtc.c struct malidp_hw_device *hwdev = malidp->dev; hwdev 37 drivers/gpu/drm/arm/malidp_crtc.c rate = clk_round_rate(hwdev->pxlclk, req_rate); hwdev 52 drivers/gpu/drm/arm/malidp_crtc.c struct malidp_hw_device *hwdev = malidp->dev; hwdev 62 drivers/gpu/drm/arm/malidp_crtc.c clk_prepare_enable(hwdev->pxlclk); hwdev 65 drivers/gpu/drm/arm/malidp_crtc.c clk_set_rate(hwdev->pxlclk, crtc->state->adjusted_mode.crtc_clock * 1000); hwdev 67 drivers/gpu/drm/arm/malidp_crtc.c hwdev->hw->modeset(hwdev, &vm); hwdev 68 drivers/gpu/drm/arm/malidp_crtc.c hwdev->hw->leave_config_mode(hwdev); hwdev 76 drivers/gpu/drm/arm/malidp_crtc.c struct malidp_hw_device *hwdev = malidp->dev; hwdev 83 drivers/gpu/drm/arm/malidp_crtc.c hwdev->hw->enter_config_mode(hwdev); hwdev 85 drivers/gpu/drm/arm/malidp_crtc.c clk_disable_unprepare(hwdev->pxlclk); hwdev 251 drivers/gpu/drm/arm/malidp_crtc.c struct malidp_hw_device *hwdev = malidp->dev; hwdev 331 drivers/gpu/drm/arm/malidp_crtc.c ret = hwdev->hw->se_calc_mclk(hwdev, s, &vm); hwdev 341 drivers/gpu/drm/arm/malidp_crtc.c struct malidp_hw_device *hwdev = malidp->dev; hwdev 381 drivers/gpu/drm/arm/malidp_crtc.c rot_mem_free = hwdev->rotation_memory[0]; hwdev 387 drivers/gpu/drm/arm/malidp_crtc.c rot_mem_free += hwdev->rotation_memory[1]; hwdev 404 drivers/gpu/drm/arm/malidp_crtc.c (hwdev->rotation_memory[1] == 0)) hwdev 407 drivers/gpu/drm/arm/malidp_crtc.c rot_mem_usable = hwdev->rotation_memory[0]; hwdev 492 drivers/gpu/drm/arm/malidp_crtc.c struct malidp_hw_device *hwdev = malidp->dev; hwdev 494 drivers/gpu/drm/arm/malidp_crtc.c malidp_hw_enable_irq(hwdev, MALIDP_DE_BLOCK, hwdev 495 drivers/gpu/drm/arm/malidp_crtc.c hwdev->hw->map.de_irq_map.vsync_irq); hwdev 502 drivers/gpu/drm/arm/malidp_crtc.c struct malidp_hw_device *hwdev = malidp->dev; hwdev 504 drivers/gpu/drm/arm/malidp_crtc.c malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK, hwdev 505 drivers/gpu/drm/arm/malidp_crtc.c hwdev->hw->map.de_irq_map.vsync_irq); hwdev 41 drivers/gpu/drm/arm/malidp_drv.c static void malidp_write_gamma_table(struct malidp_hw_device *hwdev, hwdev 52 drivers/gpu/drm/arm/malidp_drv.c malidp_hw_write(hwdev, gamma_write_mask, hwdev 53 drivers/gpu/drm/arm/malidp_drv.c hwdev->hw->map.coeffs_base + MALIDP_COEF_TABLE_ADDR); hwdev 55 drivers/gpu/drm/arm/malidp_drv.c malidp_hw_write(hwdev, data[i], hwdev 56 drivers/gpu/drm/arm/malidp_drv.c hwdev->hw->map.coeffs_base + hwdev 64 drivers/gpu/drm/arm/malidp_drv.c struct malidp_hw_device *hwdev = malidp->dev; hwdev 70 drivers/gpu/drm/arm/malidp_drv.c malidp_hw_clearbits(hwdev, hwdev 79 drivers/gpu/drm/arm/malidp_drv.c malidp_write_gamma_table(hwdev, mc->gamma_coeffs); hwdev 81 drivers/gpu/drm/arm/malidp_drv.c malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_GAMMA, hwdev 91 drivers/gpu/drm/arm/malidp_drv.c struct malidp_hw_device *hwdev = malidp->dev; hwdev 98 drivers/gpu/drm/arm/malidp_drv.c malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_CADJ, hwdev 107 drivers/gpu/drm/arm/malidp_drv.c malidp_hw_write(hwdev, hwdev 109 drivers/gpu/drm/arm/malidp_drv.c hwdev->hw->map.coeffs_base + hwdev 112 drivers/gpu/drm/arm/malidp_drv.c malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_CADJ, hwdev 123 drivers/gpu/drm/arm/malidp_drv.c struct malidp_hw_device *hwdev = malidp->dev; hwdev 126 drivers/gpu/drm/arm/malidp_drv.c u32 se_control = hwdev->hw->map.se_base + hwdev 127 drivers/gpu/drm/arm/malidp_drv.c ((hwdev->hw->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) ? hwdev 135 drivers/gpu/drm/arm/malidp_drv.c val = malidp_hw_read(hwdev, se_control); hwdev 137 drivers/gpu/drm/arm/malidp_drv.c malidp_hw_write(hwdev, val, se_control); hwdev 141 drivers/gpu/drm/arm/malidp_drv.c hwdev->hw->se_set_scaling_coeffs(hwdev, s, old_s); hwdev 142 drivers/gpu/drm/arm/malidp_drv.c val = malidp_hw_read(hwdev, se_control); hwdev 149 drivers/gpu/drm/arm/malidp_drv.c malidp_hw_write(hwdev, val, se_control); hwdev 154 drivers/gpu/drm/arm/malidp_drv.c malidp_hw_write(hwdev, val, layer_control + MALIDP_SE_L0_IN_SIZE); hwdev 157 drivers/gpu/drm/arm/malidp_drv.c malidp_hw_write(hwdev, val, layer_control + MALIDP_SE_L0_OUT_SIZE); hwdev 160 drivers/gpu/drm/arm/malidp_drv.c malidp_hw_write(hwdev, s->h_init_phase, scr + MALIDP_SE_H_INIT_PH); hwdev 161 drivers/gpu/drm/arm/malidp_drv.c malidp_hw_write(hwdev, s->h_delta_phase, scr + MALIDP_SE_H_DELTA_PH); hwdev 162 drivers/gpu/drm/arm/malidp_drv.c malidp_hw_write(hwdev, s->v_init_phase, scr + MALIDP_SE_V_INIT_PH); hwdev 163 drivers/gpu/drm/arm/malidp_drv.c malidp_hw_write(hwdev, s->v_delta_phase, scr + MALIDP_SE_V_DELTA_PH); hwdev 172 drivers/gpu/drm/arm/malidp_drv.c struct malidp_hw_device *hwdev = malidp->dev; hwdev 175 drivers/gpu/drm/arm/malidp_drv.c hwdev->hw->set_config_valid(hwdev, 1); hwdev 177 drivers/gpu/drm/arm/malidp_drv.c if (hwdev->hw->in_config_mode(hwdev)) { hwdev 393 drivers/gpu/drm/arm/malidp_drv.c struct malidp_hw_device *hwdev = malidp->dev; hwdev 397 drivers/gpu/drm/arm/malidp_drv.c drm->mode_config.min_width = hwdev->min_line_size; hwdev 398 drivers/gpu/drm/arm/malidp_drv.c drm->mode_config.min_height = hwdev->min_line_size; hwdev 399 drivers/gpu/drm/arm/malidp_drv.c drm->mode_config.max_width = hwdev->max_line_size; hwdev 400 drivers/gpu/drm/arm/malidp_drv.c drm->mode_config.max_height = hwdev->max_line_size; hwdev 430 drivers/gpu/drm/arm/malidp_drv.c struct malidp_hw_device *hwdev = malidp->dev; hwdev 450 drivers/gpu/drm/arm/malidp_drv.c malidp_de_irq_fini(hwdev); hwdev 605 drivers/gpu/drm/arm/malidp_drv.c static bool malidp_is_compatible_hw_id(struct malidp_hw_device *hwdev, hwdev 618 drivers/gpu/drm/arm/malidp_drv.c core_id = malidp_hw_read(hwdev, MALIDP500_DC_BASE + MALIDP_DE_CORE_ID); hwdev 631 drivers/gpu/drm/arm/malidp_drv.c core_id = malidp_hw_read(hwdev, hwdev 691 drivers/gpu/drm/arm/malidp_drv.c struct malidp_hw_device *hwdev = malidp->dev; hwdev 694 drivers/gpu/drm/arm/malidp_drv.c WARN_ON(!hwdev->hw->in_config_mode(hwdev)); hwdev 696 drivers/gpu/drm/arm/malidp_drv.c malidp_se_irq_fini(hwdev); hwdev 697 drivers/gpu/drm/arm/malidp_drv.c malidp_de_irq_fini(hwdev); hwdev 698 drivers/gpu/drm/arm/malidp_drv.c hwdev->pm_suspended = true; hwdev 699 drivers/gpu/drm/arm/malidp_drv.c clk_disable_unprepare(hwdev->mclk); hwdev 700 drivers/gpu/drm/arm/malidp_drv.c clk_disable_unprepare(hwdev->aclk); hwdev 701 drivers/gpu/drm/arm/malidp_drv.c clk_disable_unprepare(hwdev->pclk); hwdev 710 drivers/gpu/drm/arm/malidp_drv.c struct malidp_hw_device *hwdev = malidp->dev; hwdev 712 drivers/gpu/drm/arm/malidp_drv.c clk_prepare_enable(hwdev->pclk); hwdev 713 drivers/gpu/drm/arm/malidp_drv.c clk_prepare_enable(hwdev->aclk); hwdev 714 drivers/gpu/drm/arm/malidp_drv.c clk_prepare_enable(hwdev->mclk); hwdev 715 drivers/gpu/drm/arm/malidp_drv.c hwdev->pm_suspended = false; hwdev 716 drivers/gpu/drm/arm/malidp_drv.c malidp_de_irq_hw_init(hwdev); hwdev 717 drivers/gpu/drm/arm/malidp_drv.c malidp_se_irq_hw_init(hwdev); hwdev 727 drivers/gpu/drm/arm/malidp_drv.c struct malidp_hw_device *hwdev; hwdev 740 drivers/gpu/drm/arm/malidp_drv.c hwdev = devm_kzalloc(dev, sizeof(*hwdev), GFP_KERNEL); hwdev 741 drivers/gpu/drm/arm/malidp_drv.c if (!hwdev) hwdev 744 drivers/gpu/drm/arm/malidp_drv.c hwdev->hw = (struct malidp_hw *)of_device_get_match_data(dev); hwdev 745 drivers/gpu/drm/arm/malidp_drv.c malidp->dev = hwdev; hwdev 748 drivers/gpu/drm/arm/malidp_drv.c hwdev->regs = devm_ioremap_resource(dev, res); hwdev 749 drivers/gpu/drm/arm/malidp_drv.c if (IS_ERR(hwdev->regs)) hwdev 750 drivers/gpu/drm/arm/malidp_drv.c return PTR_ERR(hwdev->regs); hwdev 752 drivers/gpu/drm/arm/malidp_drv.c hwdev->pclk = devm_clk_get(dev, "pclk"); hwdev 753 drivers/gpu/drm/arm/malidp_drv.c if (IS_ERR(hwdev->pclk)) hwdev 754 drivers/gpu/drm/arm/malidp_drv.c return PTR_ERR(hwdev->pclk); hwdev 756 drivers/gpu/drm/arm/malidp_drv.c hwdev->aclk = devm_clk_get(dev, "aclk"); hwdev 757 drivers/gpu/drm/arm/malidp_drv.c if (IS_ERR(hwdev->aclk)) hwdev 758 drivers/gpu/drm/arm/malidp_drv.c return PTR_ERR(hwdev->aclk); hwdev 760 drivers/gpu/drm/arm/malidp_drv.c hwdev->mclk = devm_clk_get(dev, "mclk"); hwdev 761 drivers/gpu/drm/arm/malidp_drv.c if (IS_ERR(hwdev->mclk)) hwdev 762 drivers/gpu/drm/arm/malidp_drv.c return PTR_ERR(hwdev->mclk); hwdev 764 drivers/gpu/drm/arm/malidp_drv.c hwdev->pxlclk = devm_clk_get(dev, "pxlclk"); hwdev 765 drivers/gpu/drm/arm/malidp_drv.c if (IS_ERR(hwdev->pxlclk)) hwdev 766 drivers/gpu/drm/arm/malidp_drv.c return PTR_ERR(hwdev->pxlclk); hwdev 803 drivers/gpu/drm/arm/malidp_drv.c if (!malidp_is_compatible_hw_id(hwdev, dev_id)) { hwdev 808 drivers/gpu/drm/arm/malidp_drv.c ret = hwdev->hw->query_hw(hwdev); hwdev 814 drivers/gpu/drm/arm/malidp_drv.c version = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_DE_CORE_ID); hwdev 829 drivers/gpu/drm/arm/malidp_drv.c malidp_hw_write(hwdev, out_depth, hwdev->hw->map.out_depth_base); hwdev 830 drivers/gpu/drm/arm/malidp_drv.c hwdev->output_color_depth = out_depth; hwdev 891 drivers/gpu/drm/arm/malidp_drv.c malidp_se_irq_fini(hwdev); hwdev 892 drivers/gpu/drm/arm/malidp_drv.c malidp_de_irq_fini(hwdev); hwdev 922 drivers/gpu/drm/arm/malidp_drv.c struct malidp_hw_device *hwdev = malidp->dev; hwdev 928 drivers/gpu/drm/arm/malidp_drv.c malidp_se_irq_fini(hwdev); hwdev 929 drivers/gpu/drm/arm/malidp_drv.c malidp_de_irq_fini(hwdev); hwdev 51 drivers/gpu/drm/arm/malidp_drv.h struct malidp_hw_device *hwdev; hwdev 270 drivers/gpu/drm/arm/malidp_hw.c static int malidp500_query_hw(struct malidp_hw_device *hwdev) hwdev 272 drivers/gpu/drm/arm/malidp_hw.c u32 conf = malidp_hw_read(hwdev, MALIDP500_CONFIG_ID); hwdev 276 drivers/gpu/drm/arm/malidp_hw.c hwdev->min_line_size = 2; hwdev 277 drivers/gpu/drm/arm/malidp_hw.c hwdev->max_line_size = SZ_2K * ln_size_mult; hwdev 278 drivers/gpu/drm/arm/malidp_hw.c hwdev->rotation_memory[0] = SZ_1K * 64 * ln_size_mult; hwdev 279 drivers/gpu/drm/arm/malidp_hw.c hwdev->rotation_memory[1] = 0; /* no second rotation memory bank */ hwdev 284 drivers/gpu/drm/arm/malidp_hw.c static void malidp500_enter_config_mode(struct malidp_hw_device *hwdev) hwdev 288 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_setbits(hwdev, MALIDP500_DC_CONFIG_REQ, MALIDP500_DC_CONTROL); hwdev 290 drivers/gpu/drm/arm/malidp_hw.c status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS); hwdev 303 drivers/gpu/drm/arm/malidp_hw.c static void malidp500_leave_config_mode(struct malidp_hw_device *hwdev) hwdev 307 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_clearbits(hwdev, MALIDP_CFG_VALID, MALIDP500_CONFIG_VALID); hwdev 308 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_clearbits(hwdev, MALIDP500_DC_CONFIG_REQ, MALIDP500_DC_CONTROL); hwdev 310 drivers/gpu/drm/arm/malidp_hw.c status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS); hwdev 319 drivers/gpu/drm/arm/malidp_hw.c static bool malidp500_in_config_mode(struct malidp_hw_device *hwdev) hwdev 323 drivers/gpu/drm/arm/malidp_hw.c status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS); hwdev 330 drivers/gpu/drm/arm/malidp_hw.c static void malidp500_set_config_valid(struct malidp_hw_device *hwdev, u8 value) hwdev 333 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_setbits(hwdev, MALIDP_CFG_VALID, MALIDP500_CONFIG_VALID); hwdev 335 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_clearbits(hwdev, MALIDP_CFG_VALID, MALIDP500_CONFIG_VALID); hwdev 338 drivers/gpu/drm/arm/malidp_hw.c static void malidp500_modeset(struct malidp_hw_device *hwdev, struct videomode *mode) hwdev 342 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, hwdev->output_color_depth, hwdev 343 drivers/gpu/drm/arm/malidp_hw.c hwdev->hw->map.out_depth_base); hwdev 344 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_clearbits(hwdev, MALIDP500_DC_CLEAR_MASK, MALIDP500_DC_CONTROL); hwdev 350 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_setbits(hwdev, val, MALIDP500_DC_CONTROL); hwdev 360 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, val, MALIDP500_BGND_COLOR); hwdev 361 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, MALIDP_BGND_COLOR_B, MALIDP500_BGND_COLOR + 4); hwdev 365 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_H_TIMINGS); hwdev 369 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_V_TIMINGS); hwdev 373 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_SYNC_WIDTH); hwdev 376 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_HV_ACTIVE); hwdev 379 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC); hwdev 381 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC); hwdev 408 drivers/gpu/drm/arm/malidp_hw.c static int malidp500_rotmem_required(struct malidp_hw_device *hwdev, u16 w, hwdev 421 drivers/gpu/drm/arm/malidp_hw.c static void malidp500_se_write_pp_coefftab(struct malidp_hw_device *hwdev, hwdev 429 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, hwdev 433 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, MALIDP_SE_SET_COEFFTAB_DATA( hwdev 438 drivers/gpu/drm/arm/malidp_hw.c static int malidp500_se_set_scaling_coeffs(struct malidp_hw_device *hwdev, hwdev 452 drivers/gpu/drm/arm/malidp_hw.c malidp500_se_write_pp_coefftab(hwdev, hwdev 458 drivers/gpu/drm/arm/malidp_hw.c malidp500_se_write_pp_coefftab(hwdev, hwdev 462 drivers/gpu/drm/arm/malidp_hw.c malidp500_se_write_pp_coefftab(hwdev, hwdev 470 drivers/gpu/drm/arm/malidp_hw.c static long malidp500_se_calc_mclk(struct malidp_hw_device *hwdev, hwdev 494 drivers/gpu/drm/arm/malidp_hw.c ret = clk_get_rate(hwdev->mclk); hwdev 503 drivers/gpu/drm/arm/malidp_hw.c static int malidp500_enable_memwrite(struct malidp_hw_device *hwdev, hwdev 509 drivers/gpu/drm/arm/malidp_hw.c u32 de_base = malidp_get_block_base(hwdev, MALIDP_DE_BLOCK); hwdev 512 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_setbits(hwdev, MALIDP_SCALE_ENGINE_EN, de_base + MALIDP_DE_DISPLAY_FUNC); hwdev 515 drivers/gpu/drm/arm/malidp_hw.c if (hwdev->mw_state != MW_NOT_ENABLED) hwdev 516 drivers/gpu/drm/arm/malidp_hw.c hwdev->mw_state = MW_RESTART; hwdev 518 drivers/gpu/drm/arm/malidp_hw.c hwdev->mw_state = MW_START; hwdev 520 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, fmt_id, base + MALIDP_MW_FORMAT); hwdev 523 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, lower_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_LOW); hwdev 524 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, upper_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_HIGH); hwdev 525 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, pitches[1], base + MALIDP_MW_P2_STRIDE); hwdev 528 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, lower_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_LOW); hwdev 529 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, upper_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_HIGH); hwdev 530 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, pitches[0], base + MALIDP_MW_P1_STRIDE); hwdev 536 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, MALIDP_DE_H_ACTIVE(w) | MALIDP_DE_V_ACTIVE(h), hwdev 543 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, rgb2yuv_coeffs[i], hwdev 548 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_setbits(hwdev, MALIDP_SE_MEMWRITE_EN, MALIDP500_SE_CONTROL); hwdev 553 drivers/gpu/drm/arm/malidp_hw.c static void malidp500_disable_memwrite(struct malidp_hw_device *hwdev) hwdev 555 drivers/gpu/drm/arm/malidp_hw.c u32 base = malidp_get_block_base(hwdev, MALIDP_DE_BLOCK); hwdev 557 drivers/gpu/drm/arm/malidp_hw.c if (hwdev->mw_state == MW_START || hwdev->mw_state == MW_RESTART) hwdev 558 drivers/gpu/drm/arm/malidp_hw.c hwdev->mw_state = MW_STOP; hwdev 559 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_clearbits(hwdev, MALIDP_SE_MEMWRITE_EN, MALIDP500_SE_CONTROL); hwdev 560 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_clearbits(hwdev, MALIDP_SCALE_ENGINE_EN, base + MALIDP_DE_DISPLAY_FUNC); hwdev 563 drivers/gpu/drm/arm/malidp_hw.c static int malidp550_query_hw(struct malidp_hw_device *hwdev) hwdev 565 drivers/gpu/drm/arm/malidp_hw.c u32 conf = malidp_hw_read(hwdev, MALIDP550_CONFIG_ID); hwdev 568 drivers/gpu/drm/arm/malidp_hw.c hwdev->min_line_size = 2; hwdev 572 drivers/gpu/drm/arm/malidp_hw.c hwdev->max_line_size = SZ_2K; hwdev 577 drivers/gpu/drm/arm/malidp_hw.c hwdev->max_line_size = SZ_4K; hwdev 582 drivers/gpu/drm/arm/malidp_hw.c hwdev->max_line_size = 1280; hwdev 588 drivers/gpu/drm/arm/malidp_hw.c hwdev->max_line_size = 0; hwdev 592 drivers/gpu/drm/arm/malidp_hw.c hwdev->rotation_memory[0] = hwdev->rotation_memory[1] = rsize * SZ_1K; hwdev 596 drivers/gpu/drm/arm/malidp_hw.c static void malidp550_enter_config_mode(struct malidp_hw_device *hwdev) hwdev 600 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_setbits(hwdev, MALIDP550_DC_CONFIG_REQ, MALIDP550_DC_CONTROL); hwdev 602 drivers/gpu/drm/arm/malidp_hw.c status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS); hwdev 615 drivers/gpu/drm/arm/malidp_hw.c static void malidp550_leave_config_mode(struct malidp_hw_device *hwdev) hwdev 619 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_clearbits(hwdev, MALIDP_CFG_VALID, MALIDP550_CONFIG_VALID); hwdev 620 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_clearbits(hwdev, MALIDP550_DC_CONFIG_REQ, MALIDP550_DC_CONTROL); hwdev 622 drivers/gpu/drm/arm/malidp_hw.c status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS); hwdev 631 drivers/gpu/drm/arm/malidp_hw.c static bool malidp550_in_config_mode(struct malidp_hw_device *hwdev) hwdev 635 drivers/gpu/drm/arm/malidp_hw.c status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS); hwdev 642 drivers/gpu/drm/arm/malidp_hw.c static void malidp550_set_config_valid(struct malidp_hw_device *hwdev, u8 value) hwdev 645 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_setbits(hwdev, MALIDP_CFG_VALID, MALIDP550_CONFIG_VALID); hwdev 647 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_clearbits(hwdev, MALIDP_CFG_VALID, MALIDP550_CONFIG_VALID); hwdev 650 drivers/gpu/drm/arm/malidp_hw.c static void malidp550_modeset(struct malidp_hw_device *hwdev, struct videomode *mode) hwdev 654 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, hwdev->output_color_depth, hwdev 655 drivers/gpu/drm/arm/malidp_hw.c hwdev->hw->map.out_depth_base); hwdev 656 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, val, MALIDP550_DE_CONTROL); hwdev 669 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, val, MALIDP550_DE_BGND_COLOR); hwdev 673 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_H_TIMINGS); hwdev 677 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_V_TIMINGS); hwdev 685 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_SYNC_WIDTH); hwdev 688 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_HV_ACTIVE); hwdev 691 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC); hwdev 693 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC); hwdev 750 drivers/gpu/drm/arm/malidp_hw.c static int malidp550_rotmem_required(struct malidp_hw_device *hwdev, u16 w, hwdev 777 drivers/gpu/drm/arm/malidp_hw.c static int malidp650_rotmem_required(struct malidp_hw_device *hwdev, u16 w, hwdev 797 drivers/gpu/drm/arm/malidp_hw.c static int malidp550_se_set_scaling_coeffs(struct malidp_hw_device *hwdev, hwdev 806 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_clearbits(hwdev, mask, MALIDP550_SE_CONTROL); hwdev 807 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_setbits(hwdev, new_value, MALIDP550_SE_CONTROL); hwdev 811 drivers/gpu/drm/arm/malidp_hw.c static long malidp550_se_calc_mclk(struct malidp_hw_device *hwdev, hwdev 835 drivers/gpu/drm/arm/malidp_hw.c ret = clk_get_rate(hwdev->mclk); hwdev 844 drivers/gpu/drm/arm/malidp_hw.c static int malidp550_enable_memwrite(struct malidp_hw_device *hwdev, hwdev 850 drivers/gpu/drm/arm/malidp_hw.c u32 de_base = malidp_get_block_base(hwdev, MALIDP_DE_BLOCK); hwdev 853 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_setbits(hwdev, MALIDP_SCALE_ENGINE_EN, de_base + MALIDP_DE_DISPLAY_FUNC); hwdev 855 drivers/gpu/drm/arm/malidp_hw.c hwdev->mw_state = MW_ONESHOT; hwdev 857 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, fmt_id, base + MALIDP_MW_FORMAT); hwdev 860 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, lower_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_LOW); hwdev 861 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, upper_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_HIGH); hwdev 862 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, pitches[1], base + MALIDP_MW_P2_STRIDE); hwdev 865 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, lower_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_LOW); hwdev 866 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, upper_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_HIGH); hwdev 867 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, pitches[0], base + MALIDP_MW_P1_STRIDE); hwdev 873 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, MALIDP_DE_H_ACTIVE(w) | MALIDP_DE_V_ACTIVE(h), hwdev 875 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_setbits(hwdev, MALIDP550_SE_MEMWRITE_ONESHOT | MALIDP_SE_MEMWRITE_EN, hwdev 882 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, rgb2yuv_coeffs[i], hwdev 890 drivers/gpu/drm/arm/malidp_hw.c static void malidp550_disable_memwrite(struct malidp_hw_device *hwdev) hwdev 892 drivers/gpu/drm/arm/malidp_hw.c u32 base = malidp_get_block_base(hwdev, MALIDP_DE_BLOCK); hwdev 894 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_clearbits(hwdev, MALIDP550_SE_MEMWRITE_ONESHOT | MALIDP_SE_MEMWRITE_EN, hwdev 896 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_clearbits(hwdev, MALIDP_SCALE_ENGINE_EN, base + MALIDP_DE_DISPLAY_FUNC); hwdev 899 drivers/gpu/drm/arm/malidp_hw.c static int malidp650_query_hw(struct malidp_hw_device *hwdev) hwdev 901 drivers/gpu/drm/arm/malidp_hw.c u32 conf = malidp_hw_read(hwdev, MALIDP550_CONFIG_ID); hwdev 904 drivers/gpu/drm/arm/malidp_hw.c hwdev->min_line_size = 4; hwdev 910 drivers/gpu/drm/arm/malidp_hw.c hwdev->max_line_size = 0; hwdev 913 drivers/gpu/drm/arm/malidp_hw.c hwdev->max_line_size = SZ_4K; hwdev 918 drivers/gpu/drm/arm/malidp_hw.c hwdev->max_line_size = 2560; hwdev 923 drivers/gpu/drm/arm/malidp_hw.c hwdev->rotation_memory[0] = hwdev->rotation_memory[1] = rsize * SZ_1K; hwdev 1149 drivers/gpu/drm/arm/malidp_hw.c static void malidp_hw_clear_irq(struct malidp_hw_device *hwdev, u8 block, u32 irq) hwdev 1151 drivers/gpu/drm/arm/malidp_hw.c u32 base = malidp_get_block_base(hwdev, block); hwdev 1153 drivers/gpu/drm/arm/malidp_hw.c if (hwdev->hw->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) hwdev 1154 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, irq, base + MALIDP_REG_CLEARIRQ); hwdev 1156 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_write(hwdev, irq, base + MALIDP_REG_STATUS); hwdev 1163 drivers/gpu/drm/arm/malidp_hw.c struct malidp_hw_device *hwdev; hwdev 1169 drivers/gpu/drm/arm/malidp_hw.c hwdev = malidp->dev; hwdev 1170 drivers/gpu/drm/arm/malidp_hw.c hw = hwdev->hw; hwdev 1178 drivers/gpu/drm/arm/malidp_hw.c if (hwdev->pm_suspended) hwdev 1182 drivers/gpu/drm/arm/malidp_hw.c dc_status = malidp_hw_read(hwdev, hw->map.dc_base + MALIDP_REG_STATUS); hwdev 1184 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, dc_status); hwdev 1196 drivers/gpu/drm/arm/malidp_hw.c status = malidp_hw_read(hwdev, MALIDP_REG_STATUS); hwdev 1200 drivers/gpu/drm/arm/malidp_hw.c mask = malidp_hw_read(hwdev, MALIDP_REG_MASKIRQ); hwdev 1212 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, status); hwdev 1227 drivers/gpu/drm/arm/malidp_hw.c void malidp_de_irq_hw_init(struct malidp_hw_device *hwdev) hwdev 1230 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff); hwdev 1231 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff); hwdev 1232 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_disable_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff); hwdev 1233 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff); hwdev 1236 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_enable_irq(hwdev, MALIDP_DC_BLOCK, hwdev 1237 drivers/gpu/drm/arm/malidp_hw.c hwdev->hw->map.dc_irq_map.irq_mask); hwdev 1240 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_enable_irq(hwdev, MALIDP_DE_BLOCK, hwdev 1241 drivers/gpu/drm/arm/malidp_hw.c hwdev->hw->map.de_irq_map.irq_mask); hwdev 1247 drivers/gpu/drm/arm/malidp_hw.c struct malidp_hw_device *hwdev = malidp->dev; hwdev 1251 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff); hwdev 1252 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff); hwdev 1253 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_disable_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff); hwdev 1254 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff); hwdev 1264 drivers/gpu/drm/arm/malidp_hw.c malidp_de_irq_hw_init(hwdev); hwdev 1269 drivers/gpu/drm/arm/malidp_hw.c void malidp_de_irq_fini(struct malidp_hw_device *hwdev) hwdev 1271 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK, hwdev 1272 drivers/gpu/drm/arm/malidp_hw.c hwdev->hw->map.de_irq_map.irq_mask); hwdev 1273 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_disable_irq(hwdev, MALIDP_DC_BLOCK, hwdev 1274 drivers/gpu/drm/arm/malidp_hw.c hwdev->hw->map.dc_irq_map.irq_mask); hwdev 1281 drivers/gpu/drm/arm/malidp_hw.c struct malidp_hw_device *hwdev = malidp->dev; hwdev 1282 drivers/gpu/drm/arm/malidp_hw.c struct malidp_hw *hw = hwdev->hw; hwdev 1291 drivers/gpu/drm/arm/malidp_hw.c if (hwdev->pm_suspended) hwdev 1294 drivers/gpu/drm/arm/malidp_hw.c status = malidp_hw_read(hwdev, hw->map.se_base + MALIDP_REG_STATUS); hwdev 1303 drivers/gpu/drm/arm/malidp_hw.c mask = malidp_hw_read(hwdev, hw->map.se_base + MALIDP_REG_MASKIRQ); hwdev 1307 drivers/gpu/drm/arm/malidp_hw.c switch (hwdev->mw_state) { hwdev 1314 drivers/gpu/drm/arm/malidp_hw.c hwdev->mw_state = MW_NOT_ENABLED; hwdev 1321 drivers/gpu/drm/arm/malidp_hw.c hw->disable_memwrite(hwdev); hwdev 1327 drivers/gpu/drm/arm/malidp_hw.c status = malidp_hw_read(hwdev, hw->map.dc_base + MALIDP_REG_STATUS); hwdev 1330 drivers/gpu/drm/arm/malidp_hw.c hw->set_config_valid(hwdev, 1); hwdev 1335 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_clear_irq(hwdev, MALIDP_SE_BLOCK, status); hwdev 1340 drivers/gpu/drm/arm/malidp_hw.c void malidp_se_irq_hw_init(struct malidp_hw_device *hwdev) hwdev 1343 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_disable_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff); hwdev 1344 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_clear_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff); hwdev 1346 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_enable_irq(hwdev, MALIDP_SE_BLOCK, hwdev 1347 drivers/gpu/drm/arm/malidp_hw.c hwdev->hw->map.se_irq_map.irq_mask); hwdev 1358 drivers/gpu/drm/arm/malidp_hw.c struct malidp_hw_device *hwdev = malidp->dev; hwdev 1362 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_disable_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff); hwdev 1363 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_clear_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff); hwdev 1373 drivers/gpu/drm/arm/malidp_hw.c hwdev->mw_state = MW_NOT_ENABLED; hwdev 1374 drivers/gpu/drm/arm/malidp_hw.c malidp_se_irq_hw_init(hwdev); hwdev 1379 drivers/gpu/drm/arm/malidp_hw.c void malidp_se_irq_fini(struct malidp_hw_device *hwdev) hwdev 1381 drivers/gpu/drm/arm/malidp_hw.c malidp_hw_disable_irq(hwdev, MALIDP_SE_BLOCK, hwdev 1382 drivers/gpu/drm/arm/malidp_hw.c hwdev->hw->map.se_irq_map.irq_mask); hwdev 147 drivers/gpu/drm/arm/malidp_hw.h int (*query_hw)(struct malidp_hw_device *hwdev); hwdev 152 drivers/gpu/drm/arm/malidp_hw.h void (*enter_config_mode)(struct malidp_hw_device *hwdev); hwdev 157 drivers/gpu/drm/arm/malidp_hw.h void (*leave_config_mode)(struct malidp_hw_device *hwdev); hwdev 162 drivers/gpu/drm/arm/malidp_hw.h bool (*in_config_mode)(struct malidp_hw_device *hwdev); hwdev 171 drivers/gpu/drm/arm/malidp_hw.h void (*set_config_valid)(struct malidp_hw_device *hwdev, u8 value); hwdev 177 drivers/gpu/drm/arm/malidp_hw.h void (*modeset)(struct malidp_hw_device *hwdev, struct videomode *m); hwdev 183 drivers/gpu/drm/arm/malidp_hw.h int (*rotmem_required)(struct malidp_hw_device *hwdev, u16 w, u16 h, hwdev 186 drivers/gpu/drm/arm/malidp_hw.h int (*se_set_scaling_coeffs)(struct malidp_hw_device *hwdev, hwdev 190 drivers/gpu/drm/arm/malidp_hw.h long (*se_calc_mclk)(struct malidp_hw_device *hwdev, hwdev 203 drivers/gpu/drm/arm/malidp_hw.h int (*enable_memwrite)(struct malidp_hw_device *hwdev, dma_addr_t *addrs, hwdev 210 drivers/gpu/drm/arm/malidp_hw.h void (*disable_memwrite)(struct malidp_hw_device *hwdev); hwdev 256 drivers/gpu/drm/arm/malidp_hw.h static inline u32 malidp_hw_read(struct malidp_hw_device *hwdev, u32 reg) hwdev 258 drivers/gpu/drm/arm/malidp_hw.h WARN_ON(hwdev->pm_suspended); hwdev 259 drivers/gpu/drm/arm/malidp_hw.h return readl(hwdev->regs + reg); hwdev 262 drivers/gpu/drm/arm/malidp_hw.h static inline void malidp_hw_write(struct malidp_hw_device *hwdev, hwdev 265 drivers/gpu/drm/arm/malidp_hw.h WARN_ON(hwdev->pm_suspended); hwdev 266 drivers/gpu/drm/arm/malidp_hw.h writel(value, hwdev->regs + reg); hwdev 269 drivers/gpu/drm/arm/malidp_hw.h static inline void malidp_hw_setbits(struct malidp_hw_device *hwdev, hwdev 272 drivers/gpu/drm/arm/malidp_hw.h u32 data = malidp_hw_read(hwdev, reg); hwdev 275 drivers/gpu/drm/arm/malidp_hw.h malidp_hw_write(hwdev, data, reg); hwdev 278 drivers/gpu/drm/arm/malidp_hw.h static inline void malidp_hw_clearbits(struct malidp_hw_device *hwdev, hwdev 281 drivers/gpu/drm/arm/malidp_hw.h u32 data = malidp_hw_read(hwdev, reg); hwdev 284 drivers/gpu/drm/arm/malidp_hw.h malidp_hw_write(hwdev, data, reg); hwdev 287 drivers/gpu/drm/arm/malidp_hw.h static inline u32 malidp_get_block_base(struct malidp_hw_device *hwdev, hwdev 292 drivers/gpu/drm/arm/malidp_hw.h return hwdev->hw->map.se_base; hwdev 294 drivers/gpu/drm/arm/malidp_hw.h return hwdev->hw->map.dc_base; hwdev 300 drivers/gpu/drm/arm/malidp_hw.h static inline void malidp_hw_disable_irq(struct malidp_hw_device *hwdev, hwdev 303 drivers/gpu/drm/arm/malidp_hw.h u32 base = malidp_get_block_base(hwdev, block); hwdev 305 drivers/gpu/drm/arm/malidp_hw.h malidp_hw_clearbits(hwdev, irq, base + MALIDP_REG_MASKIRQ); hwdev 308 drivers/gpu/drm/arm/malidp_hw.h static inline void malidp_hw_enable_irq(struct malidp_hw_device *hwdev, hwdev 311 drivers/gpu/drm/arm/malidp_hw.h u32 base = malidp_get_block_base(hwdev, block); hwdev 313 drivers/gpu/drm/arm/malidp_hw.h malidp_hw_setbits(hwdev, irq, base + MALIDP_REG_MASKIRQ); hwdev 317 drivers/gpu/drm/arm/malidp_hw.h void malidp_se_irq_hw_init(struct malidp_hw_device *hwdev); hwdev 318 drivers/gpu/drm/arm/malidp_hw.h void malidp_de_irq_hw_init(struct malidp_hw_device *hwdev); hwdev 319 drivers/gpu/drm/arm/malidp_hw.h void malidp_de_irq_fini(struct malidp_hw_device *hwdev); hwdev 321 drivers/gpu/drm/arm/malidp_hw.h void malidp_se_irq_fini(struct malidp_hw_device *hwdev); hwdev 328 drivers/gpu/drm/arm/malidp_hw.h static inline u8 malidp_hw_get_pitch_align(struct malidp_hw_device *hwdev, bool rotated) hwdev 334 drivers/gpu/drm/arm/malidp_hw.h if (hwdev->hw->map.bus_align_bytes == 8) hwdev 337 drivers/gpu/drm/arm/malidp_hw.h return hwdev->hw->map.bus_align_bytes << (rotated ? 2 : 0); hwdev 363 drivers/gpu/drm/arm/malidp_hw.h static inline void malidp_se_set_enh_coeffs(struct malidp_hw_device *hwdev) hwdev 370 drivers/gpu/drm/arm/malidp_hw.h u32 image_enh = hwdev->hw->map.se_base + hwdev 371 drivers/gpu/drm/arm/malidp_hw.h ((hwdev->hw->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) ? hwdev 376 drivers/gpu/drm/arm/malidp_hw.h malidp_hw_write(hwdev, val, image_enh); hwdev 378 drivers/gpu/drm/arm/malidp_hw.h malidp_hw_write(hwdev, enhancer_coeffs[i], enh_coeffs + i * 4); hwdev 243 drivers/gpu/drm/arm/malidp_mw.c struct malidp_hw_device *hwdev = malidp->dev; hwdev 262 drivers/gpu/drm/arm/malidp_mw.c hwdev->hw->enable_memwrite(hwdev, mw_state->addrs, hwdev 270 drivers/gpu/drm/arm/malidp_mw.c hwdev->hw->disable_memwrite(hwdev); hwdev 520 drivers/gpu/drm/arm/malidp_planes.c ms->format = malidp_hw_get_format_id(&mp->hwdev->hw->map, hwdev 528 drivers/gpu/drm/arm/malidp_planes.c u8 alignment = malidp_hw_get_pitch_align(mp->hwdev, rotated); hwdev 549 drivers/gpu/drm/arm/malidp_planes.c if ((state->crtc_w > mp->hwdev->max_line_size) || hwdev 550 drivers/gpu/drm/arm/malidp_planes.c (state->crtc_h > mp->hwdev->max_line_size) || hwdev 551 drivers/gpu/drm/arm/malidp_planes.c (state->crtc_w < mp->hwdev->min_line_size) || hwdev 552 drivers/gpu/drm/arm/malidp_planes.c (state->crtc_h < mp->hwdev->min_line_size)) hwdev 561 drivers/gpu/drm/arm/malidp_planes.c !(mp->hwdev->hw->features & MALIDP_DEVICE_LV_HAS_3_STRIDES) && hwdev 594 drivers/gpu/drm/arm/malidp_planes.c val = mp->hwdev->hw->rotmem_required(mp->hwdev, state->crtc_w, hwdev 625 drivers/gpu/drm/arm/malidp_planes.c num_strides = (mp->hwdev->hw->features & hwdev 636 drivers/gpu/drm/arm/malidp_planes.c malidp_hw_write(mp->hwdev, pitches[i] * block_h, hwdev 690 drivers/gpu/drm/arm/malidp_planes.c malidp_hw_write(plane->hwdev, malidp_yuv2rgb_coeffs[enc][range][i], hwdev 710 drivers/gpu/drm/arm/malidp_planes.c malidp_hw_write(mp->hwdev, mmu_ctrl, hwdev 745 drivers/gpu/drm/arm/malidp_planes.c malidp_hw_write(mp->hwdev, lower_32_bits(paddr), ptr); hwdev 746 drivers/gpu/drm/arm/malidp_planes.c malidp_hw_write(mp->hwdev, upper_32_bits(paddr), ptr + 4); hwdev 762 drivers/gpu/drm/arm/malidp_planes.c malidp_hw_write(mp->hwdev, 0, mp->layer->afbc_decoder_offset); hwdev 774 drivers/gpu/drm/arm/malidp_planes.c malidp_hw_write(mp->hwdev, val, hwdev 779 drivers/gpu/drm/arm/malidp_planes.c malidp_hw_write(mp->hwdev, val, hwdev 788 drivers/gpu/drm/arm/malidp_planes.c malidp_hw_write(mp->hwdev, val, mp->layer->afbc_decoder_offset); hwdev 821 drivers/gpu/drm/arm/malidp_planes.c val = malidp_hw_read(mp->hwdev, mp->layer->base); hwdev 823 drivers/gpu/drm/arm/malidp_planes.c malidp_hw_write(mp->hwdev, val, mp->layer->base); hwdev 838 drivers/gpu/drm/arm/malidp_planes.c malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h), hwdev 841 drivers/gpu/drm/arm/malidp_planes.c malidp_hw_write(mp->hwdev, LAYER_H_VAL(dest_w) | LAYER_V_VAL(dest_h), hwdev 844 drivers/gpu/drm/arm/malidp_planes.c malidp_hw_write(mp->hwdev, LAYER_H_VAL(state->crtc_x) | hwdev 853 drivers/gpu/drm/arm/malidp_planes.c malidp_hw_write(mp->hwdev, 1, hwdev 855 drivers/gpu/drm/arm/malidp_planes.c malidp_hw_write(mp->hwdev, hwdev 863 drivers/gpu/drm/arm/malidp_planes.c val = malidp_hw_read(mp->hwdev, mp->layer->base + MALIDP_LAYER_CONTROL); hwdev 905 drivers/gpu/drm/arm/malidp_planes.c malidp_hw_write(mp->hwdev, val, hwdev 914 drivers/gpu/drm/arm/malidp_planes.c malidp_hw_clearbits(mp->hwdev, hwdev 996 drivers/gpu/drm/arm/malidp_planes.c plane->hwdev = malidp->dev; hwdev 114 drivers/hwmon/hwmon.c struct hwmon_device *hwdev = to_hwmon_device(dev); hwdev 116 drivers/hwmon/hwmon.c if (hwdev->group.attrs) hwdev 117 drivers/hwmon/hwmon.c hwmon_free_attrs(hwdev->group.attrs); hwdev 118 drivers/hwmon/hwmon.c kfree(hwdev->groups); hwdev 119 drivers/hwmon/hwmon.c kfree(hwdev); hwdev 141 drivers/hwmon/hwmon.c struct hwmon_device *hwdev = to_hwmon_device(tdata->dev); hwdev 145 drivers/hwmon/hwmon.c ret = hwdev->chip->ops->read(tdata->dev, hwmon_temp, hwmon_temp_input, hwdev 584 drivers/hwmon/hwmon.c struct hwmon_device *hwdev; hwdev 598 drivers/hwmon/hwmon.c hwdev = kzalloc(sizeof(*hwdev), GFP_KERNEL); hwdev 599 drivers/hwmon/hwmon.c if (hwdev == NULL) { hwdev 604 drivers/hwmon/hwmon.c hdev = &hwdev->dev; hwdev 614 drivers/hwmon/hwmon.c hwdev->groups = kcalloc(ngroups, sizeof(*groups), GFP_KERNEL); hwdev 615 drivers/hwmon/hwmon.c if (!hwdev->groups) { hwdev 626 drivers/hwmon/hwmon.c hwdev->group.attrs = attrs; hwdev 628 drivers/hwmon/hwmon.c hwdev->groups[ngroups++] = &hwdev->group; hwdev 632 drivers/hwmon/hwmon.c hwdev->groups[ngroups++] = groups[i]; hwdev 635 drivers/hwmon/hwmon.c hdev->groups = hwdev->groups; hwdev 640 drivers/hwmon/hwmon.c hwdev->name = name; hwdev 644 drivers/hwmon/hwmon.c hwdev->chip = chip; hwdev 784 drivers/hwmon/hwmon.c struct device *hwdev = *(struct device **)res; hwdev 786 drivers/hwmon/hwmon.c hwmon_device_unregister(hwdev); hwdev 804 drivers/hwmon/hwmon.c struct device **ptr, *hwdev; hwdev 813 drivers/hwmon/hwmon.c hwdev = hwmon_device_register_with_groups(dev, name, drvdata, groups); hwdev 814 drivers/hwmon/hwmon.c if (IS_ERR(hwdev)) hwdev 817 drivers/hwmon/hwmon.c *ptr = hwdev; hwdev 819 drivers/hwmon/hwmon.c return hwdev; hwdev 823 drivers/hwmon/hwmon.c return hwdev; hwdev 844 drivers/hwmon/hwmon.c struct device **ptr, *hwdev; hwdev 853 drivers/hwmon/hwmon.c hwdev = hwmon_device_register_with_info(dev, name, drvdata, chip, hwdev 855 drivers/hwmon/hwmon.c if (IS_ERR(hwdev)) hwdev 858 drivers/hwmon/hwmon.c *ptr = hwdev; hwdev 861 drivers/hwmon/hwmon.c return hwdev; hwdev 865 drivers/hwmon/hwmon.c return hwdev; hwdev 871 drivers/hwmon/hwmon.c struct device **hwdev = res; hwdev 873 drivers/hwmon/hwmon.c return *hwdev == data; hwdev 168 drivers/hwmon/scmi-hwmon.c struct device *hwdev, *dev = &sdev->dev; hwdev 254 drivers/hwmon/scmi-hwmon.c hwdev = devm_hwmon_device_register_with_info(dev, "scmi_sensors", hwdev 258 drivers/hwmon/scmi-hwmon.c return PTR_ERR_OR_ZERO(hwdev); hwdev 133 drivers/hwmon/scpi-hwmon.c struct device *hwdev, *dev = &pdev->dev; hwdev 242 drivers/hwmon/scpi-hwmon.c hwdev = devm_hwmon_device_register_with_groups(dev, hwdev 245 drivers/hwmon/scpi-hwmon.c if (IS_ERR(hwdev)) hwdev 246 drivers/hwmon/scpi-hwmon.c return PTR_ERR(hwdev); hwdev 59 drivers/infiniband/hw/qib/qib_user_pages.c int qib_map_page(struct pci_dev *hwdev, struct page *page, dma_addr_t *daddr) hwdev 63 drivers/infiniband/hw/qib/qib_user_pages.c phys = pci_map_page(hwdev, page, 0, PAGE_SIZE, PCI_DMA_FROMDEVICE); hwdev 64 drivers/infiniband/hw/qib/qib_user_pages.c if (pci_dma_mapping_error(hwdev, phys)) hwdev 68 drivers/infiniband/hw/qib/qib_user_pages.c pci_unmap_page(hwdev, phys, PAGE_SIZE, PCI_DMA_FROMDEVICE); hwdev 69 drivers/infiniband/hw/qib/qib_user_pages.c phys = pci_map_page(hwdev, page, 0, PAGE_SIZE, hwdev 71 drivers/infiniband/hw/qib/qib_user_pages.c if (pci_dma_mapping_error(hwdev, phys)) hwdev 52 drivers/net/ethernet/huawei/hinic/hinic_dev.h struct hinic_hwdev *hwdev; hwdev 121 drivers/net/ethernet/huawei/hinic/hinic_ethtool.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 122 drivers/net/ethernet/huawei/hinic/hinic_ethtool.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 148 drivers/net/ethernet/huawei/hinic/hinic_ethtool.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 150 drivers/net/ethernet/huawei/hinic/hinic_ethtool.c channels->max_rx = hwdev->nic_cap.max_qps; hwdev 151 drivers/net/ethernet/huawei/hinic/hinic_ethtool.c channels->max_tx = hwdev->nic_cap.max_qps; hwdev 154 drivers/net/ethernet/huawei/hinic/hinic_ethtool.c channels->rx_count = hinic_hwdev_num_qps(hwdev); hwdev 155 drivers/net/ethernet/huawei/hinic/hinic_ethtool.c channels->tx_count = hinic_hwdev_num_qps(hwdev); hwdev 787 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c static int init_cmdqs_ctxt(struct hinic_hwdev *hwdev, hwdev 790 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 808 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); hwdev 867 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c struct hinic_hwdev *hwdev; hwdev 895 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c hwdev = container_of(func_to_io, struct hinic_hwdev, func_to_io); hwdev 896 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c err = init_cmdqs_ctxt(hwdev, cmdqs, db_area); hwdev 70 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c static int get_capability(struct hinic_hwdev *hwdev, hwdev 73 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_cap *nic_cap = &hwdev->nic_cap; hwdev 76 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c if (!HINIC_IS_PF(hwdev->hwif) && !HINIC_IS_PPF(hwdev->hwif)) hwdev 82 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c num_aeqs = HINIC_HWIF_NUM_AEQS(hwdev->hwif); hwdev 83 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c num_ceqs = HINIC_HWIF_NUM_CEQS(hwdev->hwif); hwdev 84 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c num_irqs = HINIC_HWIF_NUM_IRQS(hwdev->hwif); hwdev 110 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_hwdev *hwdev = &pfhwdev->hwdev; hwdev 111 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 128 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c return get_capability(hwdev, &dev_cap); hwdev 137 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c static int get_dev_cap(struct hinic_hwdev *hwdev) hwdev 139 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 147 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); hwdev 170 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c static int init_msix(struct hinic_hwdev *hwdev) hwdev 172 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 184 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c msix_entries_size = nr_irqs * sizeof(*hwdev->msix_entries); hwdev 185 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c hwdev->msix_entries = devm_kzalloc(&pdev->dev, msix_entries_size, hwdev 187 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c if (!hwdev->msix_entries) hwdev 191 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c hwdev->msix_entries[i].entry = i; hwdev 193 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c err = pci_enable_msix_exact(pdev, hwdev->msix_entries, nr_irqs); hwdev 206 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c static void disable_msix(struct hinic_hwdev *hwdev) hwdev 208 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 225 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd, hwdev 228 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 237 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); hwdev 250 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c static int init_fw_ctxt(struct hinic_hwdev *hwdev) hwdev 252 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 266 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_FWCTXT_INIT, hwdev 286 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c static int set_hw_ioctxt(struct hinic_hwdev *hwdev, unsigned int rq_depth, hwdev 289 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 313 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); hwdev 321 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c static int wait_for_outbound_state(struct hinic_hwdev *hwdev) hwdev 324 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 342 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c static int wait_for_db_state(struct hinic_hwdev *hwdev) hwdev 344 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 369 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c static int clear_io_resources(struct hinic_hwdev *hwdev) hwdev 372 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 387 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); hwdev 408 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c static int set_resources_state(struct hinic_hwdev *hwdev, hwdev 412 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 424 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); hwdev 440 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c static int get_base_qpn(struct hinic_hwdev *hwdev, u16 *base_qpn) hwdev 443 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 450 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_GET_GLOBAL_QPN, hwdev 469 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c int hinic_hwdev_ifup(struct hinic_hwdev *hwdev) hwdev 471 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_func_to_io *func_to_io = &hwdev->func_to_io; hwdev 472 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_cap *nic_cap = &hwdev->nic_cap; hwdev 473 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 481 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c err = get_base_qpn(hwdev, &base_qpn); hwdev 490 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c ceq_msix_entries = &hwdev->msix_entries[num_aeqs]; hwdev 500 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c sq_msix_entries = &hwdev->msix_entries[num_aeqs + num_ceqs]; hwdev 501 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c rq_msix_entries = &hwdev->msix_entries[num_aeqs + num_ceqs + num_qps]; hwdev 510 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c err = wait_for_db_state(hwdev); hwdev 516 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c err = set_hw_ioctxt(hwdev, HINIC_SQ_DEPTH, HINIC_RQ_DEPTH); hwdev 537 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev) hwdev 539 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_func_to_io *func_to_io = &hwdev->func_to_io; hwdev 540 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_cap *nic_cap = &hwdev->nic_cap; hwdev 542 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c clear_io_resources(hwdev); hwdev 555 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev, hwdev 561 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 572 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); hwdev 587 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev, hwdev 590 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 601 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); hwdev 628 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_hwdev *hwdev; hwdev 633 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c hwdev = &pfhwdev->hwdev; hwdev 634 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c hwif = hwdev->hwif; hwdev 668 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_hwdev *hwdev = &pfhwdev->hwdev; hwdev 669 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 692 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_hwdev *hwdev = &pfhwdev->hwdev; hwdev 694 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c hinic_set_pf_action(hwdev->hwif, HINIC_PF_MGMT_INIT); hwdev 712 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_hwdev *hwdev; hwdev 738 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c hwdev = &pfhwdev->hwdev; hwdev 739 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c hwdev->hwif = hwif; hwdev 741 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c err = init_msix(hwdev); hwdev 747 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c err = wait_for_outbound_state(hwdev); hwdev 755 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c err = hinic_aeqs_init(&hwdev->aeqs, hwif, num_aeqs, hwdev 757 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c hwdev->msix_entries); hwdev 769 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c err = get_dev_cap(hwdev); hwdev 775 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c err = init_fw_ctxt(hwdev); hwdev 781 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c err = set_resources_state(hwdev, HINIC_RES_ACTIVE); hwdev 787 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c return hwdev; hwdev 795 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c hinic_aeqs_free(&hwdev->aeqs); hwdev 798 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c disable_msix(hwdev); hwdev 811 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c void hinic_free_hwdev(struct hinic_hwdev *hwdev) hwdev 813 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_pfhwdev *pfhwdev = container_of(hwdev, hwdev 815 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c hwdev); hwdev 817 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c set_resources_state(hwdev, HINIC_RES_CLEAN); hwdev 821 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c hinic_aeqs_free(&hwdev->aeqs); hwdev 823 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c disable_msix(hwdev); hwdev 825 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c hinic_free_hwif(hwdev->hwif); hwdev 828 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c int hinic_hwdev_max_num_qps(struct hinic_hwdev *hwdev) hwdev 830 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_cap *nic_cap = &hwdev->nic_cap; hwdev 841 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev) hwdev 843 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_cap *nic_cap = &hwdev->nic_cap; hwdev 855 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_sq *hinic_hwdev_get_sq(struct hinic_hwdev *hwdev, int i) hwdev 857 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_func_to_io *func_to_io = &hwdev->func_to_io; hwdev 860 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c if (i >= hinic_hwdev_num_qps(hwdev)) hwdev 873 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_rq *hinic_hwdev_get_rq(struct hinic_hwdev *hwdev, int i) hwdev 875 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_func_to_io *func_to_io = &hwdev->func_to_io; hwdev 878 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c if (i >= hinic_hwdev_num_qps(hwdev)) hwdev 891 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index) hwdev 893 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c return hinic_msix_attr_cnt_clear(hwdev->hwif, msix_index); hwdev 908 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index, hwdev 913 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c return hinic_msix_attr_set(hwdev->hwif, msix_index, hwdev 928 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq, hwdev 932 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 955 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c pfhwdev = container_of(hwdev, struct hinic_pfhwdev, hwdev); hwdev 970 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c void hinic_hwdev_set_msix_state(struct hinic_hwdev *hwdev, u16 msix_index, hwdev 973 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c hinic_set_msix_state(hwdev->hwif, msix_index, flag); hwdev 242 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h struct hinic_hwdev hwdev; hwdev 249 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev, hwdev 255 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev, hwdev 258 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd, hwdev 262 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h int hinic_hwdev_ifup(struct hinic_hwdev *hwdev); hwdev 264 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev); hwdev 268 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h void hinic_free_hwdev(struct hinic_hwdev *hwdev); hwdev 270 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h int hinic_hwdev_max_num_qps(struct hinic_hwdev *hwdev); hwdev 272 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev); hwdev 274 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h struct hinic_sq *hinic_hwdev_get_sq(struct hinic_hwdev *hwdev, int i); hwdev 276 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h struct hinic_rq *hinic_hwdev_get_rq(struct hinic_hwdev *hwdev, int i); hwdev 278 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index); hwdev 280 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index, hwdev 285 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq, hwdev 288 drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h void hinic_hwdev_set_msix_state(struct hinic_hwdev *hwdev, u16 msix_index, hwdev 559 drivers/net/ethernet/huawei/hinic/hinic_hw_mgmt.c struct hinic_hwdev *hwdev = &pfhwdev->hwdev; hwdev 580 drivers/net/ethernet/huawei/hinic/hinic_hw_mgmt.c hinic_aeq_register_hw_cb(&hwdev->aeqs, HINIC_MSG_FROM_MGMT_CPU, hwdev 593 drivers/net/ethernet/huawei/hinic/hinic_hw_mgmt.c struct hinic_hwdev *hwdev = &pfhwdev->hwdev; hwdev 595 drivers/net/ethernet/huawei/hinic/hinic_hw_mgmt.c hinic_aeq_unregister_hw_cb(&hwdev->aeqs, HINIC_MSG_FROM_MGMT_CPU); hwdev 117 drivers/net/ethernet/huawei/hinic/hinic_main.c int i, num_qps = hinic_hwdev_num_qps(nic_dev->hwdev); hwdev 134 drivers/net/ethernet/huawei/hinic/hinic_main.c int err, i, j, num_txqs = hinic_hwdev_num_qps(nic_dev->hwdev); hwdev 147 drivers/net/ethernet/huawei/hinic/hinic_main.c struct hinic_sq *sq = hinic_hwdev_get_sq(nic_dev->hwdev, i); hwdev 173 drivers/net/ethernet/huawei/hinic/hinic_main.c int i, num_txqs = hinic_hwdev_num_qps(nic_dev->hwdev); hwdev 194 drivers/net/ethernet/huawei/hinic/hinic_main.c int err, i, j, num_rxqs = hinic_hwdev_num_qps(nic_dev->hwdev); hwdev 207 drivers/net/ethernet/huawei/hinic/hinic_main.c struct hinic_rq *rq = hinic_hwdev_get_rq(nic_dev->hwdev, i); hwdev 233 drivers/net/ethernet/huawei/hinic/hinic_main.c int i, num_rxqs = hinic_hwdev_num_qps(nic_dev->hwdev); hwdev 250 drivers/net/ethernet/huawei/hinic/hinic_main.c err = hinic_set_max_qnum(nic_dev, nic_dev->hwdev->nic_cap.max_qps); hwdev 319 drivers/net/ethernet/huawei/hinic/hinic_main.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 320 drivers/net/ethernet/huawei/hinic/hinic_main.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 325 drivers/net/ethernet/huawei/hinic/hinic_main.c nic_dev->max_qps = hinic_hwdev_max_num_qps(hwdev); hwdev 359 drivers/net/ethernet/huawei/hinic/hinic_main.c nic_dev->num_qps = hinic_hwdev_num_qps(hwdev); hwdev 378 drivers/net/ethernet/huawei/hinic/hinic_main.c err = hinic_hwdev_ifup(nic_dev->hwdev); hwdev 478 drivers/net/ethernet/huawei/hinic/hinic_main.c hinic_hwdev_ifdown(nic_dev->hwdev); hwdev 512 drivers/net/ethernet/huawei/hinic/hinic_main.c hinic_hwdev_ifdown(nic_dev->hwdev); hwdev 936 drivers/net/ethernet/huawei/hinic/hinic_main.c struct hinic_hwdev *hwdev; hwdev 939 drivers/net/ethernet/huawei/hinic/hinic_main.c hwdev = hinic_init_hwdev(pdev); hwdev 940 drivers/net/ethernet/huawei/hinic/hinic_main.c if (IS_ERR(hwdev)) { hwdev 942 drivers/net/ethernet/huawei/hinic/hinic_main.c return PTR_ERR(hwdev); hwdev 945 drivers/net/ethernet/huawei/hinic/hinic_main.c num_qps = hinic_hwdev_num_qps(hwdev); hwdev 965 drivers/net/ethernet/huawei/hinic/hinic_main.c nic_dev->hwdev = hwdev; hwdev 1020 drivers/net/ethernet/huawei/hinic/hinic_main.c hinic_hwdev_cb_register(nic_dev->hwdev, HINIC_MGMT_MSG_CMD_LINK_STATUS, hwdev 1039 drivers/net/ethernet/huawei/hinic/hinic_main.c hinic_hwdev_cb_unregister(nic_dev->hwdev, hwdev 1054 drivers/net/ethernet/huawei/hinic/hinic_main.c hinic_free_hwdev(hwdev); hwdev 1125 drivers/net/ethernet/huawei/hinic/hinic_main.c hinic_hwdev_cb_unregister(nic_dev->hwdev, hwdev 1135 drivers/net/ethernet/huawei/hinic/hinic_main.c hinic_free_hwdev(nic_dev->hwdev); hwdev 41 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 43 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 63 drivers/net/ethernet/huawei/hinic/hinic_port.c err = hinic_port_msg_cmd(hwdev, cmd, &port_mac_cmd, hwdev 112 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 114 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 121 drivers/net/ethernet/huawei/hinic/hinic_port.c err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_GET_MAC, hwdev 144 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 146 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 165 drivers/net/ethernet/huawei/hinic/hinic_port.c err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_CHANGE_MTU, hwdev 186 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 189 drivers/net/ethernet/huawei/hinic/hinic_port.c port_vlan_cmd.func_idx = HINIC_HWIF_FUNC_IDX(hwdev->hwif); hwdev 192 drivers/net/ethernet/huawei/hinic/hinic_port.c return hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_ADD_VLAN, hwdev 206 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 209 drivers/net/ethernet/huawei/hinic/hinic_port.c port_vlan_cmd.func_idx = HINIC_HWIF_FUNC_IDX(hwdev->hwif); hwdev 212 drivers/net/ethernet/huawei/hinic/hinic_port.c return hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_DEL_VLAN, hwdev 226 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 229 drivers/net/ethernet/huawei/hinic/hinic_port.c rx_mode_cmd.func_idx = HINIC_HWIF_FUNC_IDX(hwdev->hwif); hwdev 232 drivers/net/ethernet/huawei/hinic/hinic_port.c return hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_SET_RX_MODE, hwdev 247 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 248 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 261 drivers/net/ethernet/huawei/hinic/hinic_port.c err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_GET_LINK_STATE, hwdev 283 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 285 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 297 drivers/net/ethernet/huawei/hinic/hinic_port.c err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_SET_PORT_STATE, hwdev 320 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 321 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 329 drivers/net/ethernet/huawei/hinic/hinic_port.c err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_SET_FUNC_STATE, hwdev 351 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 352 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 359 drivers/net/ethernet/huawei/hinic/hinic_port.c err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_GET_CAP, hwdev 381 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 382 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 391 drivers/net/ethernet/huawei/hinic/hinic_port.c err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_SET_TSO, hwdev 407 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 413 drivers/net/ethernet/huawei/hinic/hinic_port.c if (!hwdev) hwdev 416 drivers/net/ethernet/huawei/hinic/hinic_port.c hwif = hwdev->hwif; hwdev 421 drivers/net/ethernet/huawei/hinic/hinic_port.c err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_SET_RX_CSUM, hwdev 436 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 443 drivers/net/ethernet/huawei/hinic/hinic_port.c if (!hwdev) hwdev 446 drivers/net/ethernet/huawei/hinic/hinic_port.c hwif = hwdev->hwif; hwdev 451 drivers/net/ethernet/huawei/hinic/hinic_port.c err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_SET_RX_VLAN_OFFLOAD, hwdev 466 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 467 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 477 drivers/net/ethernet/huawei/hinic/hinic_port.c err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_SET_RQ_IQ_MAP, hwdev 493 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 494 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 505 drivers/net/ethernet/huawei/hinic/hinic_port.c err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_SET_LRO, hwdev 520 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 522 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 532 drivers/net/ethernet/huawei/hinic/hinic_port.c err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_SET_LRO_TIMER, hwdev 556 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 561 drivers/net/ethernet/huawei/hinic/hinic_port.c if (!hwdev) hwdev 584 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev; hwdev 592 drivers/net/ethernet/huawei/hinic/hinic_port.c hwdev = nic_dev->hwdev; hwdev 593 drivers/net/ethernet/huawei/hinic/hinic_port.c func_to_io = &hwdev->func_to_io; hwdev 594 drivers/net/ethernet/huawei/hinic/hinic_port.c hwif = hwdev->hwif; hwdev 653 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 654 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 662 drivers/net/ethernet/huawei/hinic/hinic_port.c err = hinic_port_msg_cmd(hwdev, hwdev 685 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev; hwdev 692 drivers/net/ethernet/huawei/hinic/hinic_port.c hwdev = nic_dev->hwdev; hwdev 693 drivers/net/ethernet/huawei/hinic/hinic_port.c func_to_io = &hwdev->func_to_io; hwdev 694 drivers/net/ethernet/huawei/hinic/hinic_port.c hwif = hwdev->hwif; hwdev 743 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 749 drivers/net/ethernet/huawei/hinic/hinic_port.c if (!hwdev || !rss_type) hwdev 752 drivers/net/ethernet/huawei/hinic/hinic_port.c hwif = hwdev->hwif; hwdev 758 drivers/net/ethernet/huawei/hinic/hinic_port.c err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_GET_RSS_CTX_TBL, hwdev 783 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 784 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 794 drivers/net/ethernet/huawei/hinic/hinic_port.c err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_SET_RSS_TEMPLATE_TBL, hwdev 811 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 817 drivers/net/ethernet/huawei/hinic/hinic_port.c if (!hwdev || !temp) hwdev 820 drivers/net/ethernet/huawei/hinic/hinic_port.c hwif = hwdev->hwif; hwdev 826 drivers/net/ethernet/huawei/hinic/hinic_port.c err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_GET_RSS_TEMPLATE_TBL, hwdev 844 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 845 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 854 drivers/net/ethernet/huawei/hinic/hinic_port.c err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_SET_RSS_HASH_ENGINE, hwdev 870 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 876 drivers/net/ethernet/huawei/hinic/hinic_port.c if (!hwdev || !type) hwdev 879 drivers/net/ethernet/huawei/hinic/hinic_port.c hwif = hwdev->hwif; hwdev 885 drivers/net/ethernet/huawei/hinic/hinic_port.c err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_GET_RSS_HASH_ENGINE, hwdev 900 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 902 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 912 drivers/net/ethernet/huawei/hinic/hinic_port.c err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_RSS_CFG, hwdev 928 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 929 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 937 drivers/net/ethernet/huawei/hinic/hinic_port.c err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_RSS_TEMP_MGR, hwdev 954 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 955 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 964 drivers/net/ethernet/huawei/hinic/hinic_port.c err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_RSS_TEMP_MGR, hwdev 981 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 982 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 991 drivers/net/ethernet/huawei/hinic/hinic_port.c err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_GET_VPORT_STAT, hwdev 1009 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 1010 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 1023 drivers/net/ethernet/huawei/hinic/hinic_port.c err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_GET_PORT_STATISTICS, hwdev 1044 drivers/net/ethernet/huawei/hinic/hinic_port.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 1051 drivers/net/ethernet/huawei/hinic/hinic_port.c if (!hwdev) hwdev 1054 drivers/net/ethernet/huawei/hinic/hinic_port.c hwif = hwdev->hwif; hwdev 1057 drivers/net/ethernet/huawei/hinic/hinic_port.c err = hinic_port_msg_cmd(hwdev, HINIC_PORT_CMD_GET_MGMT_VERSION, hwdev 132 drivers/net/ethernet/huawei/hinic/hinic_rx.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 133 drivers/net/ethernet/huawei/hinic/hinic_rx.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 169 drivers/net/ethernet/huawei/hinic/hinic_rx.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 170 drivers/net/ethernet/huawei/hinic/hinic_rx.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 435 drivers/net/ethernet/huawei/hinic/hinic_rx.c hinic_hwdev_set_msix_state(nic_dev->hwdev, hwdev 464 drivers/net/ethernet/huawei/hinic/hinic_rx.c hinic_hwdev_set_msix_state(nic_dev->hwdev, hwdev 469 drivers/net/ethernet/huawei/hinic/hinic_rx.c hinic_hwdev_msix_cnt_set(nic_dev->hwdev, rq->msix_entry); hwdev 478 drivers/net/ethernet/huawei/hinic/hinic_rx.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 485 drivers/net/ethernet/huawei/hinic/hinic_rx.c hinic_hwdev_msix_set(hwdev, rq->msix_entry, hwdev 136 drivers/net/ethernet/huawei/hinic/hinic_tx.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 137 drivers/net/ethernet/huawei/hinic/hinic_tx.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 187 drivers/net/ethernet/huawei/hinic/hinic_tx.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 188 drivers/net/ethernet/huawei/hinic/hinic_tx.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 676 drivers/net/ethernet/huawei/hinic/hinic_tx.c hinic_hwdev_set_msix_state(nic_dev->hwdev, hwdev 705 drivers/net/ethernet/huawei/hinic/hinic_tx.c hinic_hwdev_set_msix_state(nic_dev->hwdev, hwdev 709 drivers/net/ethernet/huawei/hinic/hinic_tx.c hinic_hwdev_msix_cnt_set(nic_dev->hwdev, txq->sq->msix_entry); hwdev 718 drivers/net/ethernet/huawei/hinic/hinic_tx.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 719 drivers/net/ethernet/huawei/hinic/hinic_tx.c struct hinic_hwif *hwif = hwdev->hwif; hwdev 726 drivers/net/ethernet/huawei/hinic/hinic_tx.c hinic_hwdev_msix_set(nic_dev->hwdev, sq->msix_entry, hwdev 762 drivers/net/ethernet/huawei/hinic/hinic_tx.c struct hinic_hwdev *hwdev = nic_dev->hwdev; hwdev 794 drivers/net/ethernet/huawei/hinic/hinic_tx.c err = hinic_hwdev_hw_ci_addr_set(hwdev, sq, CI_UPDATE_NO_PENDING, hwdev 450 drivers/net/ethernet/toshiba/tc35815.c struct pci_dev *hwdev, hwdev 457 drivers/net/ethernet/toshiba/tc35815.c *dma_handle = pci_map_single(hwdev, skb->data, RX_BUF_SIZE, hwdev 459 drivers/net/ethernet/toshiba/tc35815.c if (pci_dma_mapping_error(hwdev, *dma_handle)) { hwdev 467 drivers/net/ethernet/toshiba/tc35815.c static void free_rxbuf_skb(struct pci_dev *hwdev, struct sk_buff *skb, dma_addr_t dma_handle) hwdev 469 drivers/net/ethernet/toshiba/tc35815.c pci_unmap_single(hwdev, dma_handle, RX_BUF_SIZE, hwdev 677 drivers/net/ethernet/via/via-rhine.c static inline int verify_mmio(struct device *hwdev, hwdev 692 drivers/net/ethernet/via/via-rhine.c dev_err(hwdev, hwdev 902 drivers/net/ethernet/via/via-rhine.c static int rhine_init_one_common(struct device *hwdev, u32 quirks, hwdev 911 drivers/net/ethernet/via/via-rhine.c rc = dma_set_mask(hwdev, DMA_BIT_MASK(32)); hwdev 913 drivers/net/ethernet/via/via-rhine.c dev_err(hwdev, "32-bit DMA addresses not supported by the card!?\n"); hwdev 922 drivers/net/ethernet/via/via-rhine.c SET_NETDEV_DEV(dev, hwdev); hwdev 999 drivers/net/ethernet/via/via-rhine.c dev_set_drvdata(hwdev, dev); hwdev 1037 drivers/net/ethernet/via/via-rhine.c struct device *hwdev = &pdev->dev; hwdev 1082 drivers/net/ethernet/via/via-rhine.c dev_err(hwdev, "Insufficient PCI resources, aborting\n"); hwdev 1098 drivers/net/ethernet/via/via-rhine.c dev_err(hwdev, hwdev 1100 drivers/net/ethernet/via/via-rhine.c dev_name(hwdev), io_size, memaddr); hwdev 1106 drivers/net/ethernet/via/via-rhine.c rc = verify_mmio(hwdev, pioaddr, ioaddr, quirks); hwdev 1155 drivers/net/ethernet/via/via-rhine.c struct device *hwdev = dev->dev.parent; hwdev 1159 drivers/net/ethernet/via/via-rhine.c ring = dma_alloc_coherent(hwdev, hwdev 1169 drivers/net/ethernet/via/via-rhine.c rp->tx_bufs = dma_alloc_coherent(hwdev, hwdev 1174 drivers/net/ethernet/via/via-rhine.c dma_free_coherent(hwdev, hwdev 1193 drivers/net/ethernet/via/via-rhine.c struct device *hwdev = dev->dev.parent; hwdev 1195 drivers/net/ethernet/via/via-rhine.c dma_free_coherent(hwdev, hwdev 1202 drivers/net/ethernet/via/via-rhine.c dma_free_coherent(hwdev, PKT_BUF_SZ * TX_RING_SIZE, hwdev 1218 drivers/net/ethernet/via/via-rhine.c struct device *hwdev = dev->dev.parent; hwdev 1225 drivers/net/ethernet/via/via-rhine.c sd->dma = dma_map_single(hwdev, sd->skb->data, size, DMA_FROM_DEVICE); hwdev 1226 drivers/net/ethernet/via/via-rhine.c if (unlikely(dma_mapping_error(hwdev, sd->dma))) { hwdev 1298 drivers/net/ethernet/via/via-rhine.c struct device *hwdev = dev->dev.parent; hwdev 1306 drivers/net/ethernet/via/via-rhine.c dma_unmap_single(hwdev, hwdev 1340 drivers/net/ethernet/via/via-rhine.c struct device *hwdev = dev->dev.parent; hwdev 1349 drivers/net/ethernet/via/via-rhine.c dma_unmap_single(hwdev, hwdev 1785 drivers/net/ethernet/via/via-rhine.c struct device *hwdev = dev->dev.parent; hwdev 1822 drivers/net/ethernet/via/via-rhine.c dma_map_single(hwdev, skb->data, skb->len, hwdev 1824 drivers/net/ethernet/via/via-rhine.c if (dma_mapping_error(hwdev, rp->tx_skbuff_dma[entry])) { hwdev 1927 drivers/net/ethernet/via/via-rhine.c struct device *hwdev = dev->dev.parent; hwdev 1985 drivers/net/ethernet/via/via-rhine.c dma_unmap_single(hwdev, hwdev 2044 drivers/net/ethernet/via/via-rhine.c struct device *hwdev = dev->dev.parent; hwdev 2102 drivers/net/ethernet/via/via-rhine.c dma_sync_single_for_cpu(hwdev, hwdev 2111 drivers/net/ethernet/via/via-rhine.c dma_sync_single_for_device(hwdev, hwdev 2123 drivers/net/ethernet/via/via-rhine.c dma_unmap_single(hwdev, hwdev 2294 drivers/net/ethernet/via/via-rhine.c struct device *hwdev = dev->dev.parent; hwdev 2298 drivers/net/ethernet/via/via-rhine.c strlcpy(info->bus_info, dev_name(hwdev), sizeof(info->bus_info)); hwdev 853 drivers/parisc/ccio-dma.c if(!hwdev) { hwdev 872 drivers/parisc/sba_iommu.c static void *sba_alloc(struct device *hwdev, size_t size, dma_addr_t *dma_handle, hwdev 877 drivers/parisc/sba_iommu.c if (!hwdev) { hwdev 887 drivers/parisc/sba_iommu.c *dma_handle = sba_map_single(hwdev, ret, size, 0); hwdev 904 drivers/parisc/sba_iommu.c sba_free(struct device *hwdev, size_t size, void *vaddr, hwdev 907 drivers/parisc/sba_iommu.c sba_unmap_page(hwdev, dma_handle, size, 0, 0); hwdev 276 drivers/xen/swiotlb-xen.c xen_swiotlb_alloc_coherent(struct device *hwdev, size_t size, hwdev 302 drivers/xen/swiotlb-xen.c ret = xen_alloc_coherent_pages(hwdev, size, dma_handle, flags, attrs); hwdev 307 drivers/xen/swiotlb-xen.c if (hwdev && hwdev->coherent_dma_mask) hwdev 308 drivers/xen/swiotlb-xen.c dma_mask = hwdev->coherent_dma_mask; hwdev 322 drivers/xen/swiotlb-xen.c xen_free_coherent_pages(hwdev, size, ret, (dma_addr_t)phys, attrs); hwdev 332 drivers/xen/swiotlb-xen.c xen_swiotlb_free_coherent(struct device *hwdev, size_t size, void *vaddr, hwdev 339 drivers/xen/swiotlb-xen.c if (hwdev && hwdev->coherent_dma_mask) hwdev 340 drivers/xen/swiotlb-xen.c dma_mask = hwdev->coherent_dma_mask; hwdev 354 drivers/xen/swiotlb-xen.c xen_free_coherent_pages(hwdev, size, vaddr, (dma_addr_t)phys, attrs); hwdev 420 drivers/xen/swiotlb-xen.c static void xen_swiotlb_unmap_page(struct device *hwdev, dma_addr_t dev_addr, hwdev 427 drivers/xen/swiotlb-xen.c if (!dev_is_dma_coherent(hwdev) && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) hwdev 428 drivers/xen/swiotlb-xen.c xen_dma_sync_for_cpu(hwdev, dev_addr, paddr, size, dir); hwdev 432 drivers/xen/swiotlb-xen.c swiotlb_tbl_unmap_single(hwdev, paddr, size, size, dir, attrs); hwdev 466 drivers/xen/swiotlb-xen.c xen_swiotlb_unmap_sg(struct device *hwdev, struct scatterlist *sgl, int nelems, hwdev 475 drivers/xen/swiotlb-xen.c xen_swiotlb_unmap_page(hwdev, sg->dma_address, sg_dma_len(sg), hwdev 537 drivers/xen/swiotlb-xen.c xen_swiotlb_dma_supported(struct device *hwdev, u64 mask) hwdev 17 include/linux/pci-dma-compat.h pci_alloc_consistent(struct pci_dev *hwdev, size_t size, hwdev 20 include/linux/pci-dma-compat.h return dma_alloc_coherent(&hwdev->dev, size, dma_handle, GFP_ATOMIC); hwdev 24 include/linux/pci-dma-compat.h pci_zalloc_consistent(struct pci_dev *hwdev, size_t size, hwdev 27 include/linux/pci-dma-compat.h return dma_alloc_coherent(&hwdev->dev, size, dma_handle, GFP_ATOMIC); hwdev 31 include/linux/pci-dma-compat.h pci_free_consistent(struct pci_dev *hwdev, size_t size, hwdev 34 include/linux/pci-dma-compat.h dma_free_coherent(&hwdev->dev, size, vaddr, dma_handle); hwdev 38 include/linux/pci-dma-compat.h pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction) hwdev 40 include/linux/pci-dma-compat.h return dma_map_single(&hwdev->dev, ptr, size, (enum dma_data_direction)direction); hwdev 44 include/linux/pci-dma-compat.h pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, hwdev 47 include/linux/pci-dma-compat.h dma_unmap_single(&hwdev->dev, dma_addr, size, (enum dma_data_direction)direction); hwdev 51 include/linux/pci-dma-compat.h pci_map_page(struct pci_dev *hwdev, struct page *page, hwdev 54 include/linux/pci-dma-compat.h return dma_map_page(&hwdev->dev, page, offset, size, (enum dma_data_direction)direction); hwdev 58 include/linux/pci-dma-compat.h pci_unmap_page(struct pci_dev *hwdev, dma_addr_t dma_address, hwdev 61 include/linux/pci-dma-compat.h dma_unmap_page(&hwdev->dev, dma_address, size, (enum dma_data_direction)direction); hwdev 65 include/linux/pci-dma-compat.h pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, hwdev 68 include/linux/pci-dma-compat.h return dma_map_sg(&hwdev->dev, sg, nents, (enum dma_data_direction)direction); hwdev 72 include/linux/pci-dma-compat.h pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, hwdev 75 include/linux/pci-dma-compat.h dma_unmap_sg(&hwdev->dev, sg, nents, (enum dma_data_direction)direction); hwdev 79 include/linux/pci-dma-compat.h pci_dma_sync_single_for_cpu(struct pci_dev *hwdev, dma_addr_t dma_handle, hwdev 82 include/linux/pci-dma-compat.h dma_sync_single_for_cpu(&hwdev->dev, dma_handle, size, (enum dma_data_direction)direction); hwdev 86 include/linux/pci-dma-compat.h pci_dma_sync_single_for_device(struct pci_dev *hwdev, dma_addr_t dma_handle, hwdev 89 include/linux/pci-dma-compat.h dma_sync_single_for_device(&hwdev->dev, dma_handle, size, (enum dma_data_direction)direction); hwdev 93 include/linux/pci-dma-compat.h pci_dma_sync_sg_for_cpu(struct pci_dev *hwdev, struct scatterlist *sg, hwdev 96 include/linux/pci-dma-compat.h dma_sync_sg_for_cpu(&hwdev->dev, sg, nelems, (enum dma_data_direction)direction); hwdev 100 include/linux/pci-dma-compat.h pci_dma_sync_sg_for_device(struct pci_dev *hwdev, struct scatterlist *sg, hwdev 103 include/linux/pci-dma-compat.h dma_sync_sg_for_device(&hwdev->dev, sg, nelems, (enum dma_data_direction)direction); hwdev 47 include/linux/swiotlb.h extern phys_addr_t swiotlb_tbl_map_single(struct device *hwdev, hwdev 55 include/linux/swiotlb.h extern void swiotlb_tbl_unmap_single(struct device *hwdev, hwdev 62 include/linux/swiotlb.h extern void swiotlb_tbl_sync_single(struct device *hwdev, hwdev 8 include/xen/arm/page-coherent.h static inline void *xen_alloc_coherent_pages(struct device *hwdev, size_t size, hwdev 11 include/xen/arm/page-coherent.h return dma_direct_alloc(hwdev, size, dma_handle, flags, attrs); hwdev 14 include/xen/arm/page-coherent.h static inline void xen_free_coherent_pages(struct device *hwdev, size_t size, hwdev 17 include/xen/arm/page-coherent.h dma_direct_free(hwdev, size, cpu_addr, dma_handle, attrs); hwdev 28 kernel/dma/dummy.c static int dma_dummy_supported(struct device *hwdev, u64 mask) hwdev 445 kernel/dma/swiotlb.c phys_addr_t swiotlb_tbl_map_single(struct device *hwdev, hwdev 469 kernel/dma/swiotlb.c dev_warn_once(hwdev, "Invalid sizes (mapping: %zd bytes, alloc: %zd bytes)", hwdev 474 kernel/dma/swiotlb.c mask = dma_get_seg_boundary(hwdev); hwdev 556 kernel/dma/swiotlb.c dev_warn(hwdev, "swiotlb buffer is full (sz: %zd bytes), total %lu (slots), used %lu (slots)\n", hwdev 580 kernel/dma/swiotlb.c void swiotlb_tbl_unmap_single(struct device *hwdev, phys_addr_t tlb_addr, hwdev 627 kernel/dma/swiotlb.c void swiotlb_tbl_sync_single(struct device *hwdev, phys_addr_t tlb_addr,