hw_state 80 drivers/bluetooth/bluecard_cs.c unsigned long hw_state; /* Status of the hardware and LED control */ hw_state 164 drivers/bluetooth/bluecard_cs.c if (test_bit(CARD_ACTIVITY, &(info->hw_state))) { hw_state 166 drivers/bluetooth/bluecard_cs.c clear_bit(CARD_ACTIVITY, &(info->hw_state)); hw_state 183 drivers/bluetooth/bluecard_cs.c set_bit(CARD_ACTIVITY, &(info->hw_state)); hw_state 185 drivers/bluetooth/bluecard_cs.c if (test_bit(CARD_HAS_ACTIVITY_LED, &(info->hw_state))) { hw_state 505 drivers/bluetooth/bluecard_cs.c if (!test_bit(CARD_READY, &(info->hw_state))) hw_state 625 drivers/bluetooth/bluecard_cs.c if (test_bit(CARD_HAS_PCCARD_ID, &(info->hw_state))) hw_state 719 drivers/bluetooth/bluecard_cs.c set_bit(CARD_HAS_PCCARD_ID, &(info->hw_state)); hw_state 722 drivers/bluetooth/bluecard_cs.c set_bit(CARD_HAS_POWER_LED, &(info->hw_state)); hw_state 725 drivers/bluetooth/bluecard_cs.c set_bit(CARD_HAS_ACTIVITY_LED, &(info->hw_state)); hw_state 772 drivers/bluetooth/bluecard_cs.c set_bit(CARD_READY, &(info->hw_state)); hw_state 805 drivers/bluetooth/bluecard_cs.c clear_bit(CARD_READY, &(info->hw_state)); hw_state 13216 drivers/gpu/drm/i915/display/intel_display.c I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state, hw_state 16700 drivers/gpu/drm/i915/display/intel_display.c &pll->state.hw_state); hw_state 851 drivers/gpu/drm/i915/display/intel_display_types.h struct intel_dpll_hw_state hw_state; hw_state 119 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_dpll_hw_state hw_state; hw_state 124 drivers/gpu/drm/i915/display/intel_dpll_mgr.c cur_state = pll->info->funcs->get_hw_state(dev_priv, pll, &hw_state); hw_state 271 drivers/gpu/drm/i915/display/intel_dpll_mgr.c &shared_dpll[i].hw_state, hw_state 305 drivers/gpu/drm/i915/display/intel_dpll_mgr.c shared_dpll[id].hw_state = *pll_state; hw_state 369 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_dpll_hw_state *hw_state) hw_state 381 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->dpll = val; hw_state 382 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->fp0 = I915_READ(PCH_FP0(id)); hw_state 383 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->fp1 = I915_READ(PCH_FP1(id)); hw_state 395 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(PCH_FP0(id), pll->state.hw_state.fp0); hw_state 396 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(PCH_FP1(id), pll->state.hw_state.fp1); hw_state 420 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll); hw_state 431 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll); hw_state 484 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const struct intel_dpll_hw_state *hw_state) hw_state 488 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->dpll, hw_state 489 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->dpll_md, hw_state 490 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->fp0, hw_state 491 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->fp1); hw_state 506 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(WRPLL_CTL(id), pll->state.hw_state.wrpll); hw_state 514 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(SPLL_CTL, pll->state.hw_state.spll); hw_state 557 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_dpll_hw_state *hw_state) hw_state 569 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->wrpll = val; hw_state 578 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_dpll_hw_state *hw_state) hw_state 589 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->spll = val; hw_state 912 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const struct intel_dpll_hw_state *hw_state) hw_state 915 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->wrpll, hw_state->spll); hw_state 942 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_dpll_hw_state *hw_state) hw_state 995 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val |= pll->state.hw_state.ctrl1 << (id * 6); hw_state 1009 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(regs[id].cfgcr1, pll->state.hw_state.cfgcr1); hw_state 1010 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(regs[id].cfgcr2, pll->state.hw_state.cfgcr2); hw_state 1047 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_dpll_hw_state *hw_state) hw_state 1067 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; hw_state 1071 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->cfgcr1 = I915_READ(regs[id].cfgcr1); hw_state 1072 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->cfgcr2 = I915_READ(regs[id].cfgcr2); hw_state 1084 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_dpll_hw_state *hw_state) hw_state 1105 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; hw_state 1484 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const struct intel_dpll_hw_state *hw_state) hw_state 1488 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->ctrl1, hw_state 1489 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->cfgcr1, hw_state 1490 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->cfgcr2); hw_state 1538 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp |= pll->state.hw_state.ebb0; hw_state 1544 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp |= pll->state.hw_state.pll0; hw_state 1550 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp |= pll->state.hw_state.pll1; hw_state 1556 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp |= pll->state.hw_state.pll2; hw_state 1562 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp |= pll->state.hw_state.pll3; hw_state 1570 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp |= pll->state.hw_state.pll6; hw_state 1576 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp |= pll->state.hw_state.pll8; hw_state 1581 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp |= pll->state.hw_state.pll9; hw_state 1587 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp |= pll->state.hw_state.pll10; hw_state 1595 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp |= pll->state.hw_state.ebb4; hw_state 1621 drivers/gpu/drm/i915/display/intel_dpll_mgr.c temp |= pll->state.hw_state.pcsdw12; hw_state 1649 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_dpll_hw_state *hw_state) hw_state 1671 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch)); hw_state 1672 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK; hw_state 1674 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch)); hw_state 1675 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE; hw_state 1677 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll0 = I915_READ(BXT_PORT_PLL(phy, ch, 0)); hw_state 1678 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll0 &= PORT_PLL_M2_MASK; hw_state 1680 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll1 = I915_READ(BXT_PORT_PLL(phy, ch, 1)); hw_state 1681 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll1 &= PORT_PLL_N_MASK; hw_state 1683 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll2 = I915_READ(BXT_PORT_PLL(phy, ch, 2)); hw_state 1684 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; hw_state 1686 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll3 = I915_READ(BXT_PORT_PLL(phy, ch, 3)); hw_state 1687 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; hw_state 1689 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll6 = I915_READ(BXT_PORT_PLL(phy, ch, 6)); hw_state 1690 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK | hw_state 1694 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll8 = I915_READ(BXT_PORT_PLL(phy, ch, 8)); hw_state 1695 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK; hw_state 1697 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll9 = I915_READ(BXT_PORT_PLL(phy, ch, 9)); hw_state 1698 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK; hw_state 1700 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll10 = I915_READ(BXT_PORT_PLL(phy, ch, 10)); hw_state 1701 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H | hw_state 1709 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch)); hw_state 1710 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12) hw_state 1712 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pcsdw12, hw_state 1714 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD; hw_state 1920 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const struct intel_dpll_hw_state *hw_state) hw_state 1925 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->ebb0, hw_state 1926 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->ebb4, hw_state 1927 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll0, hw_state 1928 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll1, hw_state 1929 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll2, hw_state 1930 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll3, hw_state 1931 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll6, hw_state 1932 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll8, hw_state 1933 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll9, hw_state 1934 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pll10, hw_state 1935 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->pcsdw12); hw_state 1956 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const struct intel_dpll_hw_state *hw_state); hw_state 2038 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = pll->state.hw_state.cfgcr0; hw_state 2046 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) { hw_state 2047 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val = pll->state.hw_state.cfgcr1; hw_state 2137 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_dpll_hw_state *hw_state) hw_state 2156 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->cfgcr0 = val; hw_state 2160 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(id)); hw_state 2435 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const struct intel_dpll_hw_state *hw_state) hw_state 2439 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->cfgcr0, hw_state 2440 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->cfgcr1); hw_state 2877 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->dpll_hw_state = port_dpll->hw_state; hw_state 2913 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (!icl_calc_dpll_state(crtc_state, encoder, &port_dpll->hw_state)) { hw_state 2923 drivers/gpu/drm/i915/display/intel_dpll_mgr.c &port_dpll->hw_state, hw_state 2934 drivers/gpu/drm/i915/display/intel_dpll_mgr.c port_dpll->pll, &port_dpll->hw_state); hw_state 2952 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (!icl_calc_dpll_state(crtc_state, encoder, &port_dpll->hw_state)) { hw_state 2958 drivers/gpu/drm/i915/display/intel_dpll_mgr.c &port_dpll->hw_state, hw_state 2966 drivers/gpu/drm/i915/display/intel_dpll_mgr.c port_dpll->pll, &port_dpll->hw_state); hw_state 2970 drivers/gpu/drm/i915/display/intel_dpll_mgr.c if (!icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state)) { hw_state 2978 drivers/gpu/drm/i915/display/intel_dpll_mgr.c &port_dpll->hw_state, hw_state 2986 drivers/gpu/drm/i915/display/intel_dpll_mgr.c port_dpll->pll, &port_dpll->hw_state); hw_state 3044 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_dpll_hw_state *hw_state) hw_state 3061 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_refclkin_ctl = I915_READ(MG_REFCLKIN_CTL(tc_port)); hw_state 3062 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK; hw_state 3064 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_clktop2_coreclkctl1 = hw_state 3066 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_clktop2_coreclkctl1 &= hw_state 3069 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_clktop2_hsclkctl = hw_state 3071 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_clktop2_hsclkctl &= hw_state 3077 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_div0 = I915_READ(MG_PLL_DIV0(tc_port)); hw_state 3078 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_div1 = I915_READ(MG_PLL_DIV1(tc_port)); hw_state 3079 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_lf = I915_READ(MG_PLL_LF(tc_port)); hw_state 3080 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_frac_lock = I915_READ(MG_PLL_FRAC_LOCK(tc_port)); hw_state 3081 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_ssc = I915_READ(MG_PLL_SSC(tc_port)); hw_state 3083 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_bias = I915_READ(MG_PLL_BIAS(tc_port)); hw_state 3084 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_tdc_coldst_bias = hw_state 3088 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART; hw_state 3089 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_bias_mask = 0; hw_state 3091 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_tdc_coldst_bias_mask = -1U; hw_state 3092 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_bias_mask = -1U; hw_state 3095 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_tdc_coldst_bias &= hw_state->mg_pll_tdc_coldst_bias_mask; hw_state 3096 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_bias &= hw_state->mg_pll_bias_mask; hw_state 3106 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_dpll_hw_state *hw_state, hw_state 3124 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->cfgcr0 = I915_READ(TGL_DPLL_CFGCR0(id)); hw_state 3125 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->cfgcr1 = I915_READ(TGL_DPLL_CFGCR1(id)); hw_state 3128 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(4)); hw_state 3129 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(4)); hw_state 3131 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id)); hw_state 3132 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id)); hw_state 3144 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_dpll_hw_state *hw_state) hw_state 3153 drivers/gpu/drm/i915/display/intel_dpll_mgr.c return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg); hw_state 3158 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_dpll_hw_state *hw_state) hw_state 3160 drivers/gpu/drm/i915/display/intel_dpll_mgr.c return icl_pll_get_hw_state(dev_priv, pll, hw_state, TBT_PLL_ENABLE); hw_state 3166 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_dpll_hw_state *hw_state = &pll->state.hw_state; hw_state 3183 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(cfgcr0_reg, hw_state->cfgcr0); hw_state 3184 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(cfgcr1_reg, hw_state->cfgcr1); hw_state 3191 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct intel_dpll_hw_state *hw_state = &pll->state.hw_state; hw_state 3203 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val |= hw_state->mg_refclkin_ctl; hw_state 3208 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val |= hw_state->mg_clktop2_coreclkctl1; hw_state 3216 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val |= hw_state->mg_clktop2_hsclkctl; hw_state 3219 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0); hw_state 3220 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1); hw_state 3221 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(MG_PLL_LF(tc_port), hw_state->mg_pll_lf); hw_state 3222 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(MG_PLL_FRAC_LOCK(tc_port), hw_state->mg_pll_frac_lock); hw_state 3223 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc); hw_state 3226 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val &= ~hw_state->mg_pll_bias_mask; hw_state 3227 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val |= hw_state->mg_pll_bias; hw_state 3231 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val &= ~hw_state->mg_pll_tdc_coldst_bias_mask; hw_state 3232 drivers/gpu/drm/i915/display/intel_dpll_mgr.c val |= hw_state->mg_pll_tdc_coldst_bias; hw_state 3413 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const struct intel_dpll_hw_state *hw_state) hw_state 3421 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->cfgcr0, hw_state->cfgcr1, hw_state 3422 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_refclkin_ctl, hw_state 3423 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_clktop2_coreclkctl1, hw_state 3424 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_clktop2_hsclkctl, hw_state 3425 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_div0, hw_state 3426 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_div1, hw_state 3427 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_lf, hw_state 3428 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_frac_lock, hw_state 3429 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_ssc, hw_state 3430 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_bias, hw_state 3431 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->mg_pll_tdc_coldst_bias); hw_state 3641 drivers/gpu/drm/i915/display/intel_dpll_mgr.c const struct intel_dpll_hw_state *hw_state) hw_state 3644 drivers/gpu/drm/i915/display/intel_dpll_mgr.c dev_priv->dpll_mgr->dump_hw_state(dev_priv, hw_state); hw_state 3651 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->dpll, hw_state 3652 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->dpll_md, hw_state 3653 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->fp0, hw_state 3654 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->fp1); hw_state 235 drivers/gpu/drm/i915/display/intel_dpll_mgr.h struct intel_dpll_hw_state hw_state; hw_state 280 drivers/gpu/drm/i915/display/intel_dpll_mgr.h struct intel_dpll_hw_state *hw_state); hw_state 377 drivers/gpu/drm/i915/display/intel_dpll_mgr.h const struct intel_dpll_hw_state *hw_state); hw_state 2839 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll); hw_state 2841 drivers/gpu/drm/i915/i915_debugfs.c pll->state.hw_state.dpll_md); hw_state 2842 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0); hw_state 2843 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1); hw_state 2844 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll); hw_state 2845 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, " cfgcr0: 0x%08x\n", pll->state.hw_state.cfgcr0); hw_state 2846 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, " cfgcr1: 0x%08x\n", pll->state.hw_state.cfgcr1); hw_state 2848 drivers/gpu/drm/i915/i915_debugfs.c pll->state.hw_state.mg_refclkin_ctl); hw_state 2850 drivers/gpu/drm/i915/i915_debugfs.c pll->state.hw_state.mg_clktop2_coreclkctl1); hw_state 2852 drivers/gpu/drm/i915/i915_debugfs.c pll->state.hw_state.mg_clktop2_hsclkctl); hw_state 2854 drivers/gpu/drm/i915/i915_debugfs.c pll->state.hw_state.mg_pll_div0); hw_state 2856 drivers/gpu/drm/i915/i915_debugfs.c pll->state.hw_state.mg_pll_div1); hw_state 2858 drivers/gpu/drm/i915/i915_debugfs.c pll->state.hw_state.mg_pll_lf); hw_state 2860 drivers/gpu/drm/i915/i915_debugfs.c pll->state.hw_state.mg_pll_frac_lock); hw_state 2862 drivers/gpu/drm/i915/i915_debugfs.c pll->state.hw_state.mg_pll_ssc); hw_state 2864 drivers/gpu/drm/i915/i915_debugfs.c pll->state.hw_state.mg_pll_bias); hw_state 2866 drivers/gpu/drm/i915/i915_debugfs.c pll->state.hw_state.mg_pll_tdc_coldst_bias); hw_state 73 drivers/mmc/host/mvsdio.c unsigned int hw_state, count = 0; hw_state 75 drivers/mmc/host/mvsdio.c hw_state = mvsd_read(MVSD_HW_STATE); hw_state 81 drivers/mmc/host/mvsdio.c } while (!(hw_state & (1 << 13))); hw_state 84 drivers/mmc/host/mvsdio.c hw_state, count, jiffies - (t - HZ)); hw_state 1758 drivers/net/dsa/b53/b53_common.c u8 hw_state; hw_state 1763 drivers/net/dsa/b53/b53_common.c hw_state = PORT_CTRL_DIS_STATE; hw_state 1766 drivers/net/dsa/b53/b53_common.c hw_state = PORT_CTRL_LISTEN_STATE; hw_state 1769 drivers/net/dsa/b53/b53_common.c hw_state = PORT_CTRL_LEARN_STATE; hw_state 1772 drivers/net/dsa/b53/b53_common.c hw_state = PORT_CTRL_FWD_STATE; hw_state 1775 drivers/net/dsa/b53/b53_common.c hw_state = PORT_CTRL_BLOCK_STATE; hw_state 1784 drivers/net/dsa/b53/b53_common.c reg |= hw_state; hw_state 242 drivers/net/ethernet/mellanox/mlx5/core/en/reporter_rx.c u8 hw_state; hw_state 248 drivers/net/ethernet/mellanox/mlx5/core/en/reporter_rx.c err = mlx5e_query_rq_state(priv->mdev, rq->rqn, &hw_state); hw_state 272 drivers/net/ethernet/mellanox/mlx5/core/en/reporter_rx.c err = devlink_fmsg_u8_pair_put(fmsg, "HW state", hw_state); hw_state 155 drivers/net/fddi/skfp/drvfbi.c smc->hw.hw_state = STOPPED ; hw_state 178 drivers/net/fddi/skfp/drvfbi.c smc->hw.hw_state = STOPPED ; hw_state 837 drivers/net/fddi/skfp/fplustm.c smc->hw.hw_state = STOPPED ; hw_state 984 drivers/net/fddi/skfp/fplustm.c smc->hw.hw_state = STOPPED ; hw_state 987 drivers/net/fddi/skfp/fplustm.c smc->hw.hw_state = STARTED ; hw_state 83 drivers/net/fddi/skfp/h/targethw.h u_short hw_state ; /* started or stopped */ hw_state 554 drivers/net/fddi/skfp/hwmtm.c if (smc->hw.hw_state != STOPPED) { hw_state 1100 drivers/net/fddi/skfp/hwmtm.c smc->hw.hw_state = STOPPED ; hw_state 1102 drivers/net/fddi/skfp/hwmtm.c smc->hw.hw_state = STARTED ; hw_state 1467 drivers/net/fddi/skfp/hwmtm.c if (smc->hw.hw_state != STOPPED) { hw_state 2034 drivers/net/fddi/skfp/hwmtm.c if (smc->hw.hw_state != STOPPED) { hw_state 65 drivers/net/wireless/broadcom/b43/leds.c if (turn_on == led->hw_state) hw_state 67 drivers/net/wireless/broadcom/b43/leds.c led->hw_state = turn_on; hw_state 261 drivers/net/wireless/broadcom/b43/leds.c led->hw_state = true; hw_state 265 drivers/net/wireless/broadcom/b43/leds.c led->hw_state = false; hw_state 274 drivers/net/wireless/broadcom/b43/leds.c led->hw_state = false; hw_state 280 drivers/net/wireless/broadcom/b43/leds.c led->hw_state = false; hw_state 286 drivers/net/wireless/broadcom/b43/leds.c led->hw_state = false; hw_state 31 drivers/net/wireless/broadcom/b43/leds.h bool hw_state; hw_state 1271 drivers/platform/x86/thinkpad_acpi.c bool hw_state; hw_state 1304 drivers/platform/x86/thinkpad_acpi.c hw_state = tpacpi_rfk_check_hwblock_state(); hw_state 1305 drivers/platform/x86/thinkpad_acpi.c rfkill_set_hw_state(atp_rfk->rfkill, hw_state); hw_state 1318 drivers/platform/x86/thinkpad_acpi.c name, (sw_state || hw_state) ? "" : "un"); hw_state 1457 drivers/scsi/csiostor/csio_scsi.c static DEVICE_ATTR(hw_state, S_IRUGO, csio_show_hw_state, NULL); hw_state 209 drivers/usb/phy/phy-twl6030-usb.c u8 vbus_state, hw_state; hw_state 212 drivers/usb/phy/phy-twl6030-usb.c hw_state = twl6030_readb(twl, TWL6030_MODULE_ID0, STS_HW_CONDITIONS); hw_state 216 drivers/usb/phy/phy-twl6030-usb.c if (!(hw_state & STS_USB_ID)) { hw_state 251 drivers/usb/phy/phy-twl6030-usb.c u8 hw_state; hw_state 254 drivers/usb/phy/phy-twl6030-usb.c hw_state = twl6030_readb(twl, TWL6030_MODULE_ID0, STS_HW_CONDITIONS); hw_state 256 drivers/usb/phy/phy-twl6030-usb.c if (hw_state & STS_USB_ID) { hw_state 255 drivers/video/fbdev/i810/i810.h struct state_registers hw_state; hw_state 466 drivers/video/fbdev/i810/i810_main.c tmp1 = par->hw_state.dclk_2d; hw_state 472 drivers/video/fbdev/i810/i810_main.c tmp1 = par->hw_state.dclk_1d; hw_state 478 drivers/video/fbdev/i810/i810_main.c i810_writel(DCLK_0DS, mmio, par->hw_state.dclk_0ds); hw_state 486 drivers/video/fbdev/i810/i810_main.c tmp1 = par->hw_state.pixconf; hw_state 500 drivers/video/fbdev/i810/i810_main.c i810_writeb(CR_DATA_CGA, mmio, *(&(par->hw_state.cr30) + i)); hw_state 503 drivers/video/fbdev/i810/i810_main.c i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr35); hw_state 505 drivers/video/fbdev/i810/i810_main.c i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr39); hw_state 507 drivers/video/fbdev/i810/i810_main.c i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr39); hw_state 511 drivers/video/fbdev/i810/i810_main.c i = par->hw_state.cr70; hw_state 518 drivers/video/fbdev/i810/i810_main.c i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr80); hw_state 519 drivers/video/fbdev/i810/i810_main.c i810_writeb(MSR_WRITE, mmio, par->hw_state.msr); hw_state 521 drivers/video/fbdev/i810/i810_main.c i = (par->hw_state.sr01) & ~0xE0 ; hw_state 534 drivers/video/fbdev/i810/i810_main.c i810_writeb(CR_DATA_CGA, mmio, *((&par->hw_state.cr00) + i)); hw_state 538 drivers/video/fbdev/i810/i810_main.c i810_writeb(CR_DATA_CGA, mmio, *((&par->hw_state.cr10) + i)); hw_state 550 drivers/video/fbdev/i810/i810_main.c tmp |= par->hw_state.gr10; hw_state 563 drivers/video/fbdev/i810/i810_main.c tmp_word |= par->hw_state.bltcntl; hw_state 567 drivers/video/fbdev/i810/i810_main.c i810_writel(PIXCONF, mmio, par->hw_state.pixconf); hw_state 572 drivers/video/fbdev/i810/i810_main.c tmp_word |= par->hw_state.hwstam; hw_state 577 drivers/video/fbdev/i810/i810_main.c tmp_long |= par->hw_state.fw_blc; hw_state 580 drivers/video/fbdev/i810/i810_main.c i810_writel(HWS_PGA, mmio, par->hw_state.hws_pga); hw_state 581 drivers/video/fbdev/i810/i810_main.c i810_writew(IER, mmio, par->hw_state.ier); hw_state 582 drivers/video/fbdev/i810/i810_main.c i810_writew(IMR, mmio, par->hw_state.imr); hw_state 583 drivers/video/fbdev/i810/i810_main.c i810_writel(DPLYSTAS, mmio, par->hw_state.dplystas); hw_state 615 drivers/video/fbdev/i810/i810_main.c *(&(par->hw_state.cr30) + i) = i810_readb(CR_DATA_CGA, mmio); hw_state 618 drivers/video/fbdev/i810/i810_main.c par->hw_state.cr35 = i810_readb(CR_DATA_CGA, mmio); hw_state 620 drivers/video/fbdev/i810/i810_main.c par->hw_state.cr39 = i810_readb(CR_DATA_CGA, mmio); hw_state 622 drivers/video/fbdev/i810/i810_main.c par->hw_state.cr41 = i810_readb(CR_DATA_CGA, mmio); hw_state 624 drivers/video/fbdev/i810/i810_main.c par->hw_state.cr70 = i810_readb(CR_DATA_CGA, mmio); hw_state 625 drivers/video/fbdev/i810/i810_main.c par->hw_state.msr = i810_readb(MSR_READ, mmio); hw_state 627 drivers/video/fbdev/i810/i810_main.c par->hw_state.cr80 = i810_readb(CR_DATA_CGA, mmio); hw_state 629 drivers/video/fbdev/i810/i810_main.c par->hw_state.sr01 = i810_readb(SR_DATA, mmio); hw_state 639 drivers/video/fbdev/i810/i810_main.c *((&par->hw_state.cr00) + i) = i810_readb(CR_DATA_CGA, mmio); hw_state 643 drivers/video/fbdev/i810/i810_main.c *((&par->hw_state.cr10) + i) = i810_readb(CR_DATA_CGA, mmio); hw_state 651 drivers/video/fbdev/i810/i810_main.c par->hw_state.dclk_2d = i810_readl(DCLK_2D, mmio); hw_state 652 drivers/video/fbdev/i810/i810_main.c par->hw_state.dclk_1d = i810_readl(DCLK_1D, mmio); hw_state 653 drivers/video/fbdev/i810/i810_main.c par->hw_state.dclk_0ds = i810_readl(DCLK_0DS, mmio); hw_state 654 drivers/video/fbdev/i810/i810_main.c par->hw_state.pixconf = i810_readl(PIXCONF, mmio); hw_state 655 drivers/video/fbdev/i810/i810_main.c par->hw_state.fw_blc = i810_readl(FW_BLC, mmio); hw_state 656 drivers/video/fbdev/i810/i810_main.c par->hw_state.bltcntl = i810_readw(BLTCNTL, mmio); hw_state 657 drivers/video/fbdev/i810/i810_main.c par->hw_state.hwstam = i810_readw(HWSTAM, mmio); hw_state 658 drivers/video/fbdev/i810/i810_main.c par->hw_state.hws_pga = i810_readl(HWS_PGA, mmio); hw_state 659 drivers/video/fbdev/i810/i810_main.c par->hw_state.ier = i810_readw(IER, mmio); hw_state 660 drivers/video/fbdev/i810/i810_main.c par->hw_state.imr = i810_readw(IMR, mmio); hw_state 661 drivers/video/fbdev/i810/i810_main.c par->hw_state.dplystas = i810_readl(DPLYSTAS, mmio);