hw_pp              38 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 		(p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
hw_pp              44 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 		(p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
hw_pp             181 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
hw_pp             217 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 		  phys_enc->hw_pp->idx - PINGPONG_0, intr_idx);
hw_pp             261 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 		      irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
hw_pp             279 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 				      phys_enc->hw_pp->idx - PINGPONG_0,
hw_pp             291 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 				      phys_enc->hw_pp->idx - PINGPONG_0,
hw_pp             298 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 			phys_enc->hw_pp->idx - PINGPONG_0,
hw_pp             636 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	} else if (dpu_enc->num_phys_encs > ARRAY_SIZE(dpu_enc->hw_pp)) {
hw_pp             639 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 				(int) ARRAY_SIZE(dpu_enc->hw_pp));
hw_pp             662 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 			vsync_cfg.ppnumber[i] = dpu_enc->hw_pp[i]->idx;
hw_pp            1005 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 		dpu_enc->hw_pp[i] = NULL;
hw_pp            1008 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 		dpu_enc->hw_pp[i] = (struct dpu_hw_pingpong *) hw_iter.hw;
hw_pp            1042 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 			if (!dpu_enc->hw_pp[i]) {
hw_pp            1054 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 			phys->hw_pp = dpu_enc->hw_pp[i];
hw_pp            1432 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	if (!phys->hw_pp) {
hw_pp            1469 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	if (!phys->hw_pp) {
hw_pp             222 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h 	struct dpu_hw_pingpong *hw_pp;
hw_pp              82 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	if (!phys_enc || !phys_enc->hw_pp)
hw_pp              96 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 					  phys_enc->hw_pp->idx - PINGPONG_0,
hw_pp             109 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	if (!phys_enc || !phys_enc->hw_pp)
hw_pp             164 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	irq->hw_idx = phys_enc->hw_pp->idx;
hw_pp             168 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	irq->hw_idx = phys_enc->hw_pp->idx;
hw_pp             203 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	if (!phys_enc || !phys_enc->hw_pp || !phys_enc->hw_ctl)
hw_pp             215 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 		     phys_enc->hw_pp->idx - PINGPONG_0,
hw_pp             224 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 			  phys_enc->hw_pp->idx - PINGPONG_0,
hw_pp             278 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	if (!phys_enc || !phys_enc->hw_pp) {
hw_pp             296 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 		      phys_enc->hw_pp->idx - PINGPONG_0,
hw_pp             309 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 			  phys_enc->hw_pp->idx - PINGPONG_0, ret,
hw_pp             327 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 			phys_enc->hw_pp->idx - PINGPONG_0,
hw_pp             361 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	if (!phys_enc || !phys_enc->hw_pp) {
hw_pp             367 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	DPU_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0);
hw_pp             369 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	if (!phys_enc->hw_pp->ops.setup_tearcheck ||
hw_pp             370 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 		!phys_enc->hw_pp->ops.enable_tearcheck) {
hw_pp             418 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 		phys_enc->hw_pp->idx - PINGPONG_0, vsync_hz,
hw_pp             422 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 		phys_enc->hw_pp->idx - PINGPONG_0, tc_enable, tc_cfg.start_pos,
hw_pp             426 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 		phys_enc->hw_pp->idx - PINGPONG_0, tc_cfg.hw_vsync_mode,
hw_pp             430 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 		phys_enc->hw_pp->idx - PINGPONG_0, tc_cfg.sync_cfg_height,
hw_pp             433 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	phys_enc->hw_pp->ops.setup_tearcheck(phys_enc->hw_pp, &tc_cfg);
hw_pp             434 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	phys_enc->hw_pp->ops.enable_tearcheck(phys_enc->hw_pp, tc_enable);
hw_pp             443 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	if (!phys_enc || !phys_enc->hw_ctl || !phys_enc->hw_pp
hw_pp             450 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 			phys_enc->hw_pp->idx - PINGPONG_0);
hw_pp             473 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	if (!phys_enc || !phys_enc->hw_ctl || !phys_enc->hw_pp) {
hw_pp             495 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	if (!phys_enc || !phys_enc->hw_pp) {
hw_pp             500 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	DPU_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0);
hw_pp             514 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	if (!phys_enc || !phys_enc->hw_pp ||
hw_pp             515 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 			!phys_enc->hw_pp->ops.connect_external_te)
hw_pp             519 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	phys_enc->hw_pp->ops.connect_external_te(phys_enc->hw_pp, enable);
hw_pp             531 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	struct dpu_hw_pingpong *hw_pp;
hw_pp             533 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	if (!phys_enc || !phys_enc->hw_pp)
hw_pp             539 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	hw_pp = phys_enc->hw_pp;
hw_pp             540 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	if (!hw_pp->ops.get_line_count)
hw_pp             543 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	return hw_pp->ops.get_line_count(hw_pp);
hw_pp             551 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	if (!phys_enc || !phys_enc->hw_pp) {
hw_pp             556 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 		      phys_enc->hw_pp->idx - PINGPONG_0,
hw_pp             564 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	if (phys_enc->hw_pp->ops.enable_tearcheck)
hw_pp             565 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 		phys_enc->hw_pp->ops.enable_tearcheck(phys_enc->hw_pp, false);
hw_pp             595 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	if (!phys_enc || !phys_enc->hw_pp) {
hw_pp             600 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 		      phys_enc->hw_pp->idx - PINGPONG_0,
hw_pp             613 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 			  phys_enc->hw_pp->idx - PINGPONG_0);
hw_pp             617 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 			phys_enc->hw_pp->idx - PINGPONG_0,