hw_ctl            957 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	struct dpu_hw_ctl *hw_ctl[MAX_CHANNELS_PER_ENC] = { NULL };
hw_ctl           1015 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 		hw_ctl[i] = (struct dpu_hw_ctl *)hw_iter.hw;
hw_ctl           1033 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 		cstate->mixers[i].lm_ctl = hw_ctl[ctl_idx];
hw_ctl           1048 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 			if (!hw_ctl[i]) {
hw_ctl           1055 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 			phys->hw_ctl = hw_ctl[i];
hw_ctl           1437 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	ctl = phys->hw_ctl;
hw_ctl           1487 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	ctl = phys_enc->hw_ctl;
hw_ctl           1530 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	ctl = phys_enc->hw_ctl;
hw_ctl           1572 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 		ctl = phys->hw_ctl;
hw_ctl           1622 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 		if (phys && phys->hw_ctl) {
hw_ctl           1623 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 			ctl = phys->hw_ctl;
hw_ctl            221 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h 	struct dpu_hw_ctl *hw_ctl;
hw_ctl             64 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	ctl = phys_enc->hw_ctl;
hw_ctl            129 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	if (!phys_enc || !phys_enc->hw_ctl)
hw_ctl            160 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	irq->hw_idx = phys_enc->hw_ctl->idx;
hw_ctl            203 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	if (!phys_enc || !phys_enc->hw_pp || !phys_enc->hw_ctl)
hw_ctl            225 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 			  phys_enc->hw_ctl->idx - CTL_0,
hw_ctl            443 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	if (!phys_enc || !phys_enc->hw_ctl || !phys_enc->hw_pp
hw_ctl            444 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 			|| !phys_enc->hw_ctl->ops.setup_intf_cfg) {
hw_ctl            473 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	if (!phys_enc || !phys_enc->hw_ctl || !phys_enc->hw_pp) {
hw_ctl            485 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	ctl = phys_enc->hw_ctl;
hw_ctl            629 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	if (!phys_enc || !phys_enc->hw_ctl) {
hw_ctl            242 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 	if (!phys_enc || !phys_enc->hw_ctl->ops.setup_intf_cfg) {
hw_ctl            282 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 	phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
hw_ctl            291 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 	struct dpu_hw_ctl *hw_ctl;
hw_ctl            299 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 	hw_ctl = phys_enc->hw_ctl;
hw_ctl            300 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 	if (!hw_ctl)
hw_ctl            317 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 	if (hw_ctl && hw_ctl->ops.get_flush_register)
hw_ctl            318 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 		flush_register = hw_ctl->ops.get_flush_register(hw_ctl);
hw_ctl            320 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 	if (!(flush_register & hw_ctl->ops.get_pending_flush(hw_ctl)))
hw_ctl            439 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 	ctl = phys_enc->hw_ctl;
hw_ctl            523 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 	struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl;
hw_ctl            526 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 	if (!hw_ctl)
hw_ctl            530 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 		(hw_ctl->ops.get_flush_register(hw_ctl) == 0),
hw_ctl            551 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 	ctl = phys_enc->hw_ctl;
hw_ctl            580 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 	if (!phys_enc->hw_intf || !phys_enc->hw_ctl) {
hw_ctl            582 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 				phys_enc->hw_intf != 0, phys_enc->hw_ctl != 0);