hw_cpu 22 arch/arm/mach-mvebu/common.h void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr); hw_cpu 30 arch/arm/mach-mvebu/platsmp-a9.c int ret, hw_cpu; hw_cpu 40 arch/arm/mach-mvebu/platsmp-a9.c hw_cpu = cpu_logical_map(cpu); hw_cpu 44 arch/arm/mach-mvebu/platsmp-a9.c mvebu_pmsu_set_cpu_boot_addr(hw_cpu, mvebu_cortex_a9_secondary_startup); hw_cpu 53 arch/arm/mach-mvebu/platsmp-a9.c ret = mvebu_cpu_reset_deassert(hw_cpu); hw_cpu 55 arch/arm/mach-mvebu/platsmp.c int ret, hw_cpu; hw_cpu 59 arch/arm/mach-mvebu/platsmp.c hw_cpu = cpu_logical_map(cpu); hw_cpu 60 arch/arm/mach-mvebu/platsmp.c mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_xp_secondary_startup); hw_cpu 72 arch/arm/mach-mvebu/platsmp.c ret = mvebu_cpu_reset_deassert(hw_cpu); hw_cpu 196 arch/arm/mach-mvebu/platsmp.c static int mv98dx3236_resume_set_cpu_boot_addr(int hw_cpu, void *boot_addr) hw_cpu 200 arch/arm/mach-mvebu/platsmp.c WARN_ON(hw_cpu != 1); hw_cpu 221 arch/arm/mach-mvebu/platsmp.c int ret, hw_cpu; hw_cpu 223 arch/arm/mach-mvebu/platsmp.c hw_cpu = cpu_logical_map(cpu); hw_cpu 224 arch/arm/mach-mvebu/platsmp.c mv98dx3236_resume_set_cpu_boot_addr(hw_cpu, hw_cpu 237 arch/arm/mach-mvebu/platsmp.c ret = mvebu_cpu_reset_deassert(hw_cpu); hw_cpu 113 arch/arm/mach-mvebu/pmsu.c void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr) hw_cpu 116 arch/arm/mach-mvebu/pmsu.c PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu)); hw_cpu 229 arch/arm/mach-mvebu/pmsu.c unsigned int hw_cpu = cpu_logical_map(smp_processor_id()); hw_cpu 240 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); hw_cpu 247 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); hw_cpu 249 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); hw_cpu 256 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); hw_cpu 260 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu)); hw_cpu 262 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu)); hw_cpu 343 arch/arm/mach-mvebu/pmsu.c unsigned int hw_cpu = cpu_logical_map(smp_processor_id()); hw_cpu 349 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); hw_cpu 351 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); hw_cpu 354 arch/arm/mach-mvebu/pmsu.c reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); hw_cpu 359 arch/arm/mach-mvebu/pmsu.c writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); hw_cpu 366 arch/arm/mach-mvebu/pmsu.c unsigned int hw_cpu = cpu_logical_map(smp_processor_id()); hw_cpu 367 arch/arm/mach-mvebu/pmsu.c mvebu_pmsu_set_cpu_boot_addr(hw_cpu, mvebu_cpu_resume); hw_cpu 164 arch/powerpc/kernel/setup_32.c unsigned int i, hw_cpu; hw_cpu 170 arch/powerpc/kernel/setup_32.c hw_cpu = get_hard_smp_processor_id(i); hw_cpu 172 arch/powerpc/kernel/setup_32.c hw_cpu = 0; hw_cpu 175 arch/powerpc/kernel/setup_32.c critirq_ctx[hw_cpu] = alloc_stack(); hw_cpu 177 arch/powerpc/kernel/setup_32.c dbgirq_ctx[hw_cpu] = alloc_stack(); hw_cpu 178 arch/powerpc/kernel/setup_32.c mcheckirq_ctx[hw_cpu] = alloc_stack(); hw_cpu 195 arch/powerpc/platforms/85xx/smp.c int hw_cpu = get_hard_smp_processor_id(cpu); hw_cpu 243 arch/powerpc/platforms/85xx/smp.c hw_cpu); hw_cpu 250 arch/powerpc/platforms/85xx/smp.c out_be32(&spin_table->pir, hw_cpu); hw_cpu 277 arch/powerpc/platforms/cell/interrupt.c static void __init init_one_iic(unsigned int hw_cpu, unsigned long addr, hw_cpu 283 arch/powerpc/platforms/cell/interrupt.c struct iic *iic = &per_cpu(cpu_iic, hw_cpu); hw_cpu 288 arch/powerpc/platforms/cell/interrupt.c iic->target_id = ((hw_cpu & 2) << 3) | ((hw_cpu & 1) ? 0xf : 0xe); hw_cpu 294 arch/powerpc/platforms/cell/interrupt.c hw_cpu, iic->target_id, node); hw_cpu 29 arch/powerpc/sysdev/fsl_rcpm.c int hw_cpu = get_hard_smp_processor_id(cpu); hw_cpu 30 arch/powerpc/sysdev/fsl_rcpm.c unsigned int mask = 1 << hw_cpu; hw_cpu 40 arch/powerpc/sysdev/fsl_rcpm.c int hw_cpu = get_hard_smp_processor_id(cpu); hw_cpu 41 arch/powerpc/sysdev/fsl_rcpm.c unsigned int mask = 1 << hw_cpu; hw_cpu 51 arch/powerpc/sysdev/fsl_rcpm.c int hw_cpu = get_hard_smp_processor_id(cpu); hw_cpu 52 arch/powerpc/sysdev/fsl_rcpm.c unsigned int mask = 1 << hw_cpu; hw_cpu 62 arch/powerpc/sysdev/fsl_rcpm.c int hw_cpu = get_hard_smp_processor_id(cpu); hw_cpu 63 arch/powerpc/sysdev/fsl_rcpm.c unsigned int mask = 1 << hw_cpu; hw_cpu 89 arch/powerpc/sysdev/fsl_rcpm.c int hw_cpu = get_hard_smp_processor_id(cpu); hw_cpu 90 arch/powerpc/sysdev/fsl_rcpm.c unsigned int mask = 1 << hw_cpu; hw_cpu 107 arch/powerpc/sysdev/fsl_rcpm.c int hw_cpu = get_hard_smp_processor_id(cpu); hw_cpu 113 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v2_regs->tph10setr0, 1 << hw_cpu); hw_cpu 166 arch/powerpc/sysdev/fsl_rcpm.c int hw_cpu = get_hard_smp_processor_id(cpu); hw_cpu 167 arch/powerpc/sysdev/fsl_rcpm.c unsigned int mask = 1 << hw_cpu; hw_cpu 190 arch/powerpc/sysdev/fsl_rcpm.c int hw_cpu = get_hard_smp_processor_id(cpu); hw_cpu 195 arch/powerpc/sysdev/fsl_rcpm.c setbits32(&rcpm_v2_regs->tph10clrr0, 1 << hw_cpu); hw_cpu 61 arch/powerpc/sysdev/xics/icp-hv.c int hw_cpu = get_hard_smp_processor_id(n_cpu); hw_cpu 66 arch/powerpc/sysdev/xics/icp-hv.c rc = plpar_hcall_norets(H_IPI, hw_cpu, value); hw_cpu 69 arch/powerpc/sysdev/xics/icp-hv.c "returned %ld\n", __func__, n_cpu, hw_cpu, value, rc); hw_cpu 23 arch/powerpc/sysdev/xics/icp-opal.c int hw_cpu = hard_smp_processor_id(); hw_cpu 26 arch/powerpc/sysdev/xics/icp-opal.c opal_int_set_mfrr(hw_cpu, 0xff); hw_cpu 127 arch/powerpc/sysdev/xics/icp-opal.c int hw_cpu = get_hard_smp_processor_id(cpu); hw_cpu 130 arch/powerpc/sysdev/xics/icp-opal.c opal_int_set_mfrr(hw_cpu, IPI_PRIORITY); hw_cpu 183 arch/powerpc/sysdev/xics/xics-common.c int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id(); hw_cpu 188 arch/powerpc/sysdev/xics/xics-common.c if (hw_cpu == xics_default_server) hw_cpu 236 arch/powerpc/sysdev/xics/xics-common.c if (server != hw_cpu) hw_cpu 529 arch/powerpc/sysdev/xive/spapr.c int hw_cpu = get_hard_smp_processor_id(cpu); hw_cpu 531 arch/powerpc/sysdev/xive/spapr.c rc = plpar_int_set_queue_config(0, hw_cpu, prio, 0, 0); hw_cpu 534 arch/powerpc/sysdev/xive/spapr.c hw_cpu, prio);