hw_cfg            217 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	const struct mdp5_cfg_hw *hw_cfg;
hw_cfg            235 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
hw_cfg            617 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	const struct mdp5_cfg_hw *hw_cfg;
hw_cfg            651 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
hw_cfg            657 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	if (mode->hdisplay > hw_cfg->lm.max_width)
hw_cfg            678 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	if ((cnt + start - 1) >= hw_cfg->lm.nb_stages) {
hw_cfg            686 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 			pstates[i].state->stage = hw_cfg->lm.nb_stages;
hw_cfg            684 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	const struct mdp5_cfg_hw *hw_cfg = mdp5_cfg_get_hw_config(cfg_hnd);
hw_cfg            687 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	const struct mdp5_ctl_block *ctl_cfg = &hw_cfg->ctl;
hw_cfg            707 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	ctl_mgr->nlm = hw_cfg->lm.count;
hw_cfg            736 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 	for (c = 0; c < ARRAY_SIZE(hw_cfg->intf.connect); c++)
hw_cfg            737 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 		if (hw_cfg->intf.connect[c] == INTF_DSI)
hw_cfg            360 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num)
hw_cfg            362 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 	const enum mdp5_intf_type *intfs = hw_cfg->intf.connect;
hw_cfg            363 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 	const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect);
hw_cfg            427 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 		const struct mdp5_cfg_hw *hw_cfg =
hw_cfg            429 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 		int dsi_id = get_dsi_id_from_intf(hw_cfg, intf->num);
hw_cfg            469 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 	const struct mdp5_cfg_hw *hw_cfg;
hw_cfg            475 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 	hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
hw_cfg            839 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 	const struct mdp5_cfg_hw *hw_cfg;
hw_cfg            842 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 	hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
hw_cfg            845 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 	ret = construct_pipes(mdp5_kms, hw_cfg->pipe_rgb.count, rgb_planes,
hw_cfg            846 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 			hw_cfg->pipe_rgb.base, hw_cfg->pipe_rgb.caps);
hw_cfg            851 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 	ret = construct_pipes(mdp5_kms, hw_cfg->pipe_vig.count, vig_planes,
hw_cfg            852 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 			hw_cfg->pipe_vig.base, hw_cfg->pipe_vig.caps);
hw_cfg            857 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 	ret = construct_pipes(mdp5_kms, hw_cfg->pipe_dma.count, dma_planes,
hw_cfg            858 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 			hw_cfg->pipe_dma.base, hw_cfg->pipe_dma.caps);
hw_cfg            863 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 	ret = construct_pipes(mdp5_kms, hw_cfg->pipe_cursor.count,
hw_cfg            864 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 			cursor_planes, hw_cfg->pipe_cursor.base,
hw_cfg            865 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 			hw_cfg->pipe_cursor.caps);
hw_cfg            875 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 	const struct mdp5_cfg_hw *hw_cfg;
hw_cfg            878 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 	hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
hw_cfg            880 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 	for (i = 0; i < hw_cfg->lm.count; i++) {
hw_cfg            883 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 		mixer = mdp5_mixer_init(&hw_cfg->lm.instances[i]);
hw_cfg            901 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 	const struct mdp5_cfg_hw *hw_cfg;
hw_cfg            905 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 	hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
hw_cfg            906 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 	intf_types = hw_cfg->intf.connect;
hw_cfg            908 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 	for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) {
hw_cfg            853 drivers/net/ethernet/atheros/alx/hw.c 	u32 cfg, hw_cfg;
hw_cfg            857 drivers/net/ethernet/atheros/alx/hw.c 	hw_cfg = alx_get_phy_config(hw);
hw_cfg            859 drivers/net/ethernet/atheros/alx/hw.c 	if (hw_cfg == ALX_DRV_PHY_UNKNOWN)
hw_cfg            862 drivers/net/ethernet/atheros/alx/hw.c 	return cfg == hw_cfg;