hubps             524 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
hubps            1215 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			split_pipe->plane_res.hubp = pool->hubps[i];
hubps            1618 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			pipe_ctx->plane_res.hubp = pool->hubps[i];
hubps            1888 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		pipe_ctx->plane_res.hubp = pool->hubps[tg_inst];
hubps             136 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct hubp *hubp = pool->hubps[i];
hubps             168 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
hubps             173 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,
hubps             193 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
hubps             200 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,
hubps             225 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
hubps             230 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,
hubps             620 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct hubp *hubp = dc->res_pool->hubps[0];
hubps             640 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct hubp *hubp = dc->res_pool->hubps[0];
hubps             650 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		if (!dc->res_pool->hubps[i]->power_gated)
hubps            1127 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		struct hubp *hubp = dc->res_pool->hubps[i];
hubps            2876 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		if (res_pool->hubps[i]->inst == mpcc_inst)
hubps            2877 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			return res_pool->hubps[i];
hubps             134 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 		struct hubp *hubp = pool->hubps[i];
hubps             204 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 		struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
hubps             212 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 				pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,
hubps             249 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 		struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
hubps             260 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 				pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,
hubps             303 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 		struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
hubps             311 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 				pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,
hubps             510 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 		struct hubp *hubp = pool->hubps[i];
hubps             916 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		if (pool->base.hubps[i] != NULL) {
hubps             917 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 			kfree(TO_DCN10_HUBP(pool->base.hubps[i]));
hubps             918 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 			pool->base.hubps[i] = NULL;
hubps            1110 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
hubps            1454 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		pool->base.hubps[j] = dcn10_hubp_create(ctx, i);
hubps            1455 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		if (pool->base.hubps[j] == NULL) {
hubps            2058 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		struct hubp *hubp = dc->res_pool->hubps[i];
hubps            1337 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (pool->base.hubps[i] != NULL) {
hubps            1338 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
hubps            1339 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			pool->base.hubps[i] = NULL;
hubps            1734 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
hubps            1814 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
hubps            2953 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
hubps            3619 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		pool->base.hubps[i] = dcn20_hubp_create(ctx, i);
hubps            3620 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		if (pool->base.hubps[i] == NULL) {
hubps             865 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		if (pool->base.hubps[i] != NULL) {
hubps             866 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
hubps             867 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 			pool->base.hubps[i] = NULL;
hubps            1548 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		pool->base.hubps[i] = dcn21_hubp_create(ctx, i);
hubps            1549 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		if (pool->base.hubps[i] == NULL) {
hubps             166 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct hubp *hubps[MAX_PIPES];