hsync_start_x      88 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	u32 hsync_start_x, hsync_end_x;
hsync_start_x     113 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	hsync_start_x = p->h_back_porch + p->hsync_pulse_width;
hsync_start_x     117 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 		active_h_start = hsync_start_x;
hsync_start_x     143 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	display_hctl = (hsync_end_x << 16) | hsync_start_x;
hsync_start_x      46 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c 	uint32_t hsync_start_x, hsync_end_x;
hsync_start_x      61 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c 	hsync_start_x = (mode->htotal - mode->hsync_start);
hsync_start_x      75 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c 			MDP4_DSI_DISPLAY_HCTRL_START(hsync_start_x) |
hsync_start_x      92 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c 	uint32_t hsync_start_x, hsync_end_x;
hsync_start_x     111 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c 	hsync_start_x = (mode->htotal - mode->hsync_start);
hsync_start_x     125 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c 			MDP4_DTV_DISPLAY_HCTRL_START(hsync_start_x) |
hsync_start_x     263 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 	uint32_t hsync_start_x, hsync_end_x;
hsync_start_x     282 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 	hsync_start_x = (mode->htotal - mode->hsync_start);
hsync_start_x     296 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 			MDP4_LCDC_DISPLAY_HCTRL_START(hsync_start_x) |
hsync_start_x     104 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	uint32_t hsync_start_x, hsync_end_x;
hsync_start_x     147 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	hsync_start_x = (mode->htotal - mode->hsync_start);
hsync_start_x     173 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 			MDP5_INTF_DISPLAY_HCTL_START(hsync_start_x) |