hsync_pulse_width 2296 drivers/gpu/drm/drm_edid.c 	unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
hsync_pulse_width 2313 drivers/gpu/drm/drm_edid.c 	if (!hsync_pulse_width || !vsync_pulse_width) {
hsync_pulse_width 2338 drivers/gpu/drm/drm_edid.c 	mode->hsync_end = mode->hsync_start + hsync_pulse_width;
hsync_pulse_width  154 drivers/gpu/drm/gma500/intel_bios.c 		dvo_timing->hsync_pulse_width;
hsync_pulse_width  302 drivers/gpu/drm/gma500/intel_bios.h 	u8 hsync_pulse_width;
hsync_pulse_width   78 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 	timing->hsync_pulse_width = mode->hsync_end - mode->hsync_start;
hsync_pulse_width  110 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 	    timing->hsync_pulse_width;
hsync_pulse_width   98 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	hsync_period = p->hsync_pulse_width + p->h_back_porch + p->width +
hsync_pulse_width  109 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 		display_v_start += p->hsync_pulse_width + p->h_back_porch;
hsync_pulse_width  113 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	hsync_start_x = p->h_back_porch + p->hsync_pulse_width;
hsync_pulse_width  142 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width;
hsync_pulse_width   26 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h 	u32 hsync_pulse_width;