hsync_period 86 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c u32 hsync_period, vsync_period; hsync_period 98 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c hsync_period = p->hsync_pulse_width + p->h_back_porch + p->width + hsync_period 104 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c hsync_period) + p->hsync_skew; hsync_period 105 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c display_v_end = ((vsync_period - p->v_front_porch) * hsync_period) + hsync_period 114 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c hsync_end_x = hsync_period - p->h_front_porch - 1; hsync_period 126 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c active_v_end = active_v_start + (p->yres * hsync_period) - 1; hsync_period 142 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width; hsync_period 170 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c DPU_REG_WRITE(c, INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period); hsync_period 172 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c p->vsync_pulse_width * hsync_period);