hsync_end_x        88 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	u32 hsync_start_x, hsync_end_x;
hsync_end_x       114 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	hsync_end_x = hsync_period - p->h_front_porch - 1;
hsync_end_x       143 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	display_hctl = (hsync_end_x << 16) | hsync_start_x;
hsync_end_x        46 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c 	uint32_t hsync_start_x, hsync_end_x;
hsync_end_x        62 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c 	hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1;
hsync_end_x        76 drivers/gpu/drm/msm/disp/mdp4/mdp4_dsi_encoder.c 			MDP4_DSI_DISPLAY_HCTRL_END(hsync_end_x));
hsync_end_x        92 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c 	uint32_t hsync_start_x, hsync_end_x;
hsync_end_x       112 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c 	hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1;
hsync_end_x       126 drivers/gpu/drm/msm/disp/mdp4/mdp4_dtv_encoder.c 			MDP4_DTV_DISPLAY_HCTRL_END(hsync_end_x));
hsync_end_x       263 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 	uint32_t hsync_start_x, hsync_end_x;
hsync_end_x       283 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 	hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1;
hsync_end_x       297 drivers/gpu/drm/msm/disp/mdp4/mdp4_lcdc_encoder.c 			MDP4_LCDC_DISPLAY_HCTRL_END(hsync_end_x));
hsync_end_x       104 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	uint32_t hsync_start_x, hsync_end_x;
hsync_end_x       148 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 	hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1;
hsync_end_x       174 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c 			MDP5_INTF_DISPLAY_HCTL_END(hsync_end_x));