hpllcc             96 drivers/gpu/drm/i915/display/intel_cdclk.c 	u16 hpllcc = 0;
hpllcc            109 drivers/gpu/drm/i915/display/intel_cdclk.c 				 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
hpllcc            114 drivers/gpu/drm/i915/display/intel_cdclk.c 	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {