hpd_offsets        64 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c static const u32 hpd_offsets[] =
hpd_offsets       289 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
hpd_offsets       313 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
hpd_offsets       318 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
hpd_offsets       348 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 			tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
hpd_offsets       350 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 			WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
hpd_offsets       354 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
hpd_offsets       356 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
hpd_offsets       358 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
hpd_offsets       365 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
hpd_offsets       393 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
hpd_offsets       395 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
hpd_offsets      3024 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
hpd_offsets      3026 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
hpd_offsets      3029 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
hpd_offsets      3031 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
hpd_offsets      3174 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
hpd_offsets      3176 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
hpd_offsets        64 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c static const u32 hpd_offsets[] =
hpd_offsets       307 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
hpd_offsets       331 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
hpd_offsets       336 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
hpd_offsets       366 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 			tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
hpd_offsets       368 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 			WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
hpd_offsets       372 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
hpd_offsets       374 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
hpd_offsets       376 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
hpd_offsets       383 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
hpd_offsets       410 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
hpd_offsets       412 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
hpd_offsets      3150 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
hpd_offsets      3152 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
hpd_offsets      3155 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
hpd_offsets      3157 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
hpd_offsets      3300 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
hpd_offsets      3302 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
hpd_offsets        67 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c static const u32 hpd_offsets[] =
hpd_offsets       241 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
hpd_offsets       264 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
hpd_offsets       269 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
hpd_offsets       292 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
hpd_offsets       294 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
hpd_offsets       303 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 			tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
hpd_offsets       305 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 			WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
hpd_offsets       335 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
hpd_offsets       337 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
hpd_offsets      2864 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
hpd_offsets      2866 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
hpd_offsets      2869 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
hpd_offsets      2871 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
hpd_offsets      3058 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
hpd_offsets      3060 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
hpd_offsets        64 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c static const u32 hpd_offsets[] =
hpd_offsets       234 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) &
hpd_offsets       258 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
hpd_offsets       263 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
hpd_offsets       286 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
hpd_offsets       288 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
hpd_offsets       297 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 			tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
hpd_offsets       299 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 			WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
hpd_offsets       328 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
hpd_offsets       330 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
hpd_offsets      2956 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
hpd_offsets      2958 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
hpd_offsets      2961 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
hpd_offsets      2963 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
hpd_offsets      3150 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
hpd_offsets      3152 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);