hi_cfg_bridge_delay 2245 drivers/media/dvb-frontends/drx39xyj/drxj.c hi_cmd.param3 = ext_attr->hi_cfg_bridge_delay; hi_cfg_bridge_delay 2417 drivers/media/dvb-frontends/drx39xyj/drxj.c ext_attr->hi_cfg_bridge_delay = hi_cfg_bridge_delay 2421 drivers/media/dvb-frontends/drx39xyj/drxj.c if ((ext_attr->hi_cfg_bridge_delay) > SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) hi_cfg_bridge_delay 2422 drivers/media/dvb-frontends/drx39xyj/drxj.c ext_attr->hi_cfg_bridge_delay = SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; hi_cfg_bridge_delay 2424 drivers/media/dvb-frontends/drx39xyj/drxj.c ext_attr->hi_cfg_bridge_delay += ((ext_attr->hi_cfg_bridge_delay) << hi_cfg_bridge_delay 445 drivers/media/dvb-frontends/drx39xyj/drxj.h u16 hi_cfg_bridge_delay; /*< HI Configure() parameter 3 */ hi_cfg_bridge_delay 118 drivers/media/dvb-frontends/drxd_hard.c u16 hi_cfg_bridge_delay; hi_cfg_bridge_delay 990 drivers/media/dvb-frontends/drxd_hard.c Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0); hi_cfg_bridge_delay 2574 drivers/media/dvb-frontends/drxd_hard.c state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) *