hi3516cv300_gate_clks   85 drivers/clk/hisilicon/crg-hi3516cv300.c static const struct hisi_gate_clock hi3516cv300_gate_clks[] = {
hi3516cv300_gate_clks  149 drivers/clk/hisilicon/crg-hi3516cv300.c 	ret = hisi_clk_register_gate(hi3516cv300_gate_clks,
hi3516cv300_gate_clks  150 drivers/clk/hisilicon/crg-hi3516cv300.c 			ARRAY_SIZE(hi3516cv300_gate_clks), clk_data);
hi3516cv300_gate_clks  162 drivers/clk/hisilicon/crg-hi3516cv300.c 	hisi_clk_unregister_gate(hi3516cv300_gate_clks,
hi3516cv300_gate_clks  163 drivers/clk/hisilicon/crg-hi3516cv300.c 				ARRAY_SIZE(hi3516cv300_gate_clks), clk_data);
hi3516cv300_gate_clks  179 drivers/clk/hisilicon/crg-hi3516cv300.c 	hisi_clk_unregister_gate(hi3516cv300_gate_clks,
hi3516cv300_gate_clks  180 drivers/clk/hisilicon/crg-hi3516cv300.c 			ARRAY_SIZE(hi3516cv300_gate_clks), crg->clk_data);