hdlcd              41 drivers/gpu/drm/arm/hdlcd_crtc.c 	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
hdlcd              44 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
hdlcd              50 drivers/gpu/drm/arm/hdlcd_crtc.c 	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
hdlcd              51 drivers/gpu/drm/arm/hdlcd_crtc.c 	unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
hdlcd              53 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask | HDLCD_INTERRUPT_VSYNC);
hdlcd              60 drivers/gpu/drm/arm/hdlcd_crtc.c 	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
hdlcd              61 drivers/gpu/drm/arm/hdlcd_crtc.c 	unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
hdlcd              63 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC);
hdlcd              85 drivers/gpu/drm/arm/hdlcd_crtc.c 	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
hdlcd             103 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_PIXEL_FORMAT, (btpp - 1) << 3);
hdlcd             115 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_RED_SELECT, format->red.offset |
hdlcd             120 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_GREEN_SELECT, format->green.offset |
hdlcd             122 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_BLUE_SELECT, format->blue.offset |
hdlcd             130 drivers/gpu/drm/arm/hdlcd_crtc.c 	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
hdlcd             150 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_BUS_OPTIONS,
hdlcd             153 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_V_DATA, m->crtc_vdisplay - 1);
hdlcd             154 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_V_BACK_PORCH, vm.vback_porch - 1);
hdlcd             155 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_V_FRONT_PORCH, vm.vfront_porch - 1);
hdlcd             156 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_V_SYNC, vm.vsync_len - 1);
hdlcd             157 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_H_DATA, m->crtc_hdisplay - 1);
hdlcd             158 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_H_BACK_PORCH, vm.hback_porch - 1);
hdlcd             159 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_H_FRONT_PORCH, vm.hfront_porch - 1);
hdlcd             160 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_H_SYNC, vm.hsync_len - 1);
hdlcd             161 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_POLARITIES, polarities);
hdlcd             167 drivers/gpu/drm/arm/hdlcd_crtc.c 	clk_set_rate(hdlcd->clk, m->crtc_clock * 1000);
hdlcd             173 drivers/gpu/drm/arm/hdlcd_crtc.c 	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
hdlcd             175 drivers/gpu/drm/arm/hdlcd_crtc.c 	clk_prepare_enable(hdlcd->clk);
hdlcd             177 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1);
hdlcd             184 drivers/gpu/drm/arm/hdlcd_crtc.c 	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
hdlcd             187 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
hdlcd             188 drivers/gpu/drm/arm/hdlcd_crtc.c 	clk_disable_unprepare(hdlcd->clk);
hdlcd             194 drivers/gpu/drm/arm/hdlcd_crtc.c 	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
hdlcd             197 drivers/gpu/drm/arm/hdlcd_crtc.c 	rate = clk_round_rate(hdlcd->clk, clk_rate);
hdlcd             262 drivers/gpu/drm/arm/hdlcd_crtc.c 	struct hdlcd_drm_private *hdlcd;
hdlcd             272 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd = plane->dev->dev_private;
hdlcd             273 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, fb->pitches[0]);
hdlcd             274 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_PITCH, fb->pitches[0]);
hdlcd             275 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_COUNT, dest_h - 1);
hdlcd             276 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd_write(hdlcd, HDLCD_REG_FB_BASE, scanout_start);
hdlcd             295 drivers/gpu/drm/arm/hdlcd_crtc.c 	struct hdlcd_drm_private *hdlcd = drm->dev_private;
hdlcd             315 drivers/gpu/drm/arm/hdlcd_crtc.c 	hdlcd->plane = plane;
hdlcd             322 drivers/gpu/drm/arm/hdlcd_crtc.c 	struct hdlcd_drm_private *hdlcd = drm->dev_private;
hdlcd             330 drivers/gpu/drm/arm/hdlcd_crtc.c 	ret = drm_crtc_init_with_planes(drm, &hdlcd->crtc, primary, NULL,
hdlcd             335 drivers/gpu/drm/arm/hdlcd_crtc.c 	drm_crtc_helper_add(&hdlcd->crtc, &hdlcd_crtc_helper_funcs);
hdlcd              43 drivers/gpu/drm/arm/hdlcd_drv.c 	struct hdlcd_drm_private *hdlcd = drm->dev_private;
hdlcd              49 drivers/gpu/drm/arm/hdlcd_drv.c 	hdlcd->clk = devm_clk_get(drm->dev, "pxlclk");
hdlcd              50 drivers/gpu/drm/arm/hdlcd_drv.c 	if (IS_ERR(hdlcd->clk))
hdlcd              51 drivers/gpu/drm/arm/hdlcd_drv.c 		return PTR_ERR(hdlcd->clk);
hdlcd              54 drivers/gpu/drm/arm/hdlcd_drv.c 	atomic_set(&hdlcd->buffer_underrun_count, 0);
hdlcd              55 drivers/gpu/drm/arm/hdlcd_drv.c 	atomic_set(&hdlcd->bus_error_count, 0);
hdlcd              56 drivers/gpu/drm/arm/hdlcd_drv.c 	atomic_set(&hdlcd->vsync_count, 0);
hdlcd              57 drivers/gpu/drm/arm/hdlcd_drv.c 	atomic_set(&hdlcd->dma_end_count, 0);
hdlcd              61 drivers/gpu/drm/arm/hdlcd_drv.c 	hdlcd->mmio = devm_ioremap_resource(drm->dev, res);
hdlcd              62 drivers/gpu/drm/arm/hdlcd_drv.c 	if (IS_ERR(hdlcd->mmio)) {
hdlcd              64 drivers/gpu/drm/arm/hdlcd_drv.c 		ret = PTR_ERR(hdlcd->mmio);
hdlcd              65 drivers/gpu/drm/arm/hdlcd_drv.c 		hdlcd->mmio = NULL;
hdlcd              69 drivers/gpu/drm/arm/hdlcd_drv.c 	version = hdlcd_read(hdlcd, HDLCD_REG_VERSION);
hdlcd             102 drivers/gpu/drm/arm/hdlcd_drv.c 	drm_crtc_cleanup(&hdlcd->crtc);
hdlcd             128 drivers/gpu/drm/arm/hdlcd_drv.c 	struct hdlcd_drm_private *hdlcd = drm->dev_private;
hdlcd             131 drivers/gpu/drm/arm/hdlcd_drv.c 	irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS);
hdlcd             135 drivers/gpu/drm/arm/hdlcd_drv.c 		atomic_inc(&hdlcd->buffer_underrun_count);
hdlcd             138 drivers/gpu/drm/arm/hdlcd_drv.c 		atomic_inc(&hdlcd->dma_end_count);
hdlcd             141 drivers/gpu/drm/arm/hdlcd_drv.c 		atomic_inc(&hdlcd->bus_error_count);
hdlcd             144 drivers/gpu/drm/arm/hdlcd_drv.c 		atomic_inc(&hdlcd->vsync_count);
hdlcd             148 drivers/gpu/drm/arm/hdlcd_drv.c 		drm_crtc_handle_vblank(&hdlcd->crtc);
hdlcd             151 drivers/gpu/drm/arm/hdlcd_drv.c 	hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status);
hdlcd             158 drivers/gpu/drm/arm/hdlcd_drv.c 	struct hdlcd_drm_private *hdlcd = drm->dev_private;
hdlcd             160 drivers/gpu/drm/arm/hdlcd_drv.c 	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, 0);
hdlcd             161 drivers/gpu/drm/arm/hdlcd_drv.c 	hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, ~0);
hdlcd             167 drivers/gpu/drm/arm/hdlcd_drv.c 	struct hdlcd_drm_private *hdlcd = drm->dev_private;
hdlcd             168 drivers/gpu/drm/arm/hdlcd_drv.c 	unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
hdlcd             173 drivers/gpu/drm/arm/hdlcd_drv.c 	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
hdlcd             180 drivers/gpu/drm/arm/hdlcd_drv.c 	struct hdlcd_drm_private *hdlcd = drm->dev_private;
hdlcd             182 drivers/gpu/drm/arm/hdlcd_drv.c 	unsigned long irq_mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
hdlcd             192 drivers/gpu/drm/arm/hdlcd_drv.c 	hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, irq_mask);
hdlcd             200 drivers/gpu/drm/arm/hdlcd_drv.c 	struct hdlcd_drm_private *hdlcd = drm->dev_private;
hdlcd             202 drivers/gpu/drm/arm/hdlcd_drv.c 	seq_printf(m, "underrun : %d\n", atomic_read(&hdlcd->buffer_underrun_count));
hdlcd             203 drivers/gpu/drm/arm/hdlcd_drv.c 	seq_printf(m, "dma_end  : %d\n", atomic_read(&hdlcd->dma_end_count));
hdlcd             204 drivers/gpu/drm/arm/hdlcd_drv.c 	seq_printf(m, "bus_error: %d\n", atomic_read(&hdlcd->bus_error_count));
hdlcd             205 drivers/gpu/drm/arm/hdlcd_drv.c 	seq_printf(m, "vsync    : %d\n", atomic_read(&hdlcd->vsync_count));
hdlcd             213 drivers/gpu/drm/arm/hdlcd_drv.c 	struct hdlcd_drm_private *hdlcd = drm->dev_private;
hdlcd             214 drivers/gpu/drm/arm/hdlcd_drv.c 	unsigned long clkrate = clk_get_rate(hdlcd->clk);
hdlcd             215 drivers/gpu/drm/arm/hdlcd_drv.c 	unsigned long mode_clock = hdlcd->crtc.mode.crtc_clock * 1000;
hdlcd             267 drivers/gpu/drm/arm/hdlcd_drv.c 	struct hdlcd_drm_private *hdlcd;
hdlcd             270 drivers/gpu/drm/arm/hdlcd_drv.c 	hdlcd = devm_kzalloc(dev, sizeof(*hdlcd), GFP_KERNEL);
hdlcd             271 drivers/gpu/drm/arm/hdlcd_drv.c 	if (!hdlcd)
hdlcd             278 drivers/gpu/drm/arm/hdlcd_drv.c 	drm->dev_private = hdlcd;
hdlcd             287 drivers/gpu/drm/arm/hdlcd_drv.c 	hdlcd->crtc.port = of_graph_get_port_by_id(dev->of_node, 0);
hdlcd             326 drivers/gpu/drm/arm/hdlcd_drv.c 	of_node_put(hdlcd->crtc.port);
hdlcd             327 drivers/gpu/drm/arm/hdlcd_drv.c 	hdlcd->crtc.port = NULL;
hdlcd             341 drivers/gpu/drm/arm/hdlcd_drv.c 	struct hdlcd_drm_private *hdlcd = drm->dev_private;
hdlcd             346 drivers/gpu/drm/arm/hdlcd_drv.c 	of_node_put(hdlcd->crtc.port);
hdlcd             347 drivers/gpu/drm/arm/hdlcd_drv.c 	hdlcd->crtc.port = NULL;
hdlcd             349 drivers/gpu/drm/arm/hdlcd_drv.c 	drm_crtc_vblank_off(&hdlcd->crtc);
hdlcd              24 drivers/gpu/drm/arm/hdlcd_drv.h static inline void hdlcd_write(struct hdlcd_drm_private *hdlcd,
hdlcd              27 drivers/gpu/drm/arm/hdlcd_drv.h 	writel(value, hdlcd->mmio + reg);
hdlcd              30 drivers/gpu/drm/arm/hdlcd_drv.h static inline u32 hdlcd_read(struct hdlcd_drm_private *hdlcd, unsigned int reg)
hdlcd              32 drivers/gpu/drm/arm/hdlcd_drv.h 	return readl(hdlcd->mmio + reg);
hdlcd              36 drivers/gpu/drm/arm/hdlcd_drv.h void hdlcd_set_scanout(struct hdlcd_drm_private *hdlcd);