hctl1            1091 drivers/gpu/drm/i915/display/intel_tv.c 	u32 tv_ctl, hctl1, hctl3, vctl1, vctl2, tmp;
hctl1            1100 drivers/gpu/drm/i915/display/intel_tv.c 	hctl1 = I915_READ(TV_H_CTL_1);
hctl1            1105 drivers/gpu/drm/i915/display/intel_tv.c 	tv_mode.htotal = (hctl1 & TV_HTOTAL_MASK) >> TV_HTOTAL_SHIFT;
hctl1            1106 drivers/gpu/drm/i915/display/intel_tv.c 	tv_mode.hsync_end = (hctl1 & TV_HSYNC_END_MASK) >> TV_HSYNC_END_SHIFT;
hctl1            1342 drivers/gpu/drm/i915/display/intel_tv.c 	u32 hctl1, hctl2, hctl3;
hctl1            1345 drivers/gpu/drm/i915/display/intel_tv.c 	hctl1 = (tv_mode->hsync_end << TV_HSYNC_END_SHIFT) |
hctl1            1384 drivers/gpu/drm/i915/display/intel_tv.c 	I915_WRITE(TV_H_CTL_1, hctl1);