hbsc              191 drivers/gpu/drm/zte/zx_plane.c 	void __iomem *hbsc = zplane->hbsc;
hbsc              252 drivers/gpu/drm/zte/zx_plane.c 	zx_writel_mask(hbsc + HBSC_CTRL0, HBSC_CTRL_EN, HBSC_CTRL_EN);
hbsc              263 drivers/gpu/drm/zte/zx_plane.c 	void __iomem *hbsc = zplane->hbsc;
hbsc              268 drivers/gpu/drm/zte/zx_plane.c 	zx_writel_mask(hbsc + HBSC_CTRL0, HBSC_CTRL_EN, 0);
hbsc              357 drivers/gpu/drm/zte/zx_plane.c 	void __iomem *hbsc = zplane->hbsc;
hbsc              428 drivers/gpu/drm/zte/zx_plane.c 	zx_writel_mask(hbsc + HBSC_CTRL0, HBSC_CTRL_EN, HBSC_CTRL_EN);
hbsc              479 drivers/gpu/drm/zte/zx_plane.c 	void __iomem *hbsc = zplane->hbsc;
hbsc              485 drivers/gpu/drm/zte/zx_plane.c 	zx_writel(hbsc + HBSC_SATURATION, 0x200);
hbsc              486 drivers/gpu/drm/zte/zx_plane.c 	zx_writel(hbsc + HBSC_HUE, 0x0);
hbsc              487 drivers/gpu/drm/zte/zx_plane.c 	zx_writel(hbsc + HBSC_BRIGHT, 0x0);
hbsc              488 drivers/gpu/drm/zte/zx_plane.c 	zx_writel(hbsc + HBSC_CONTRAST, 0x200);
hbsc              490 drivers/gpu/drm/zte/zx_plane.c 	zx_writel(hbsc + HBSC_THRESHOLD_COL1, (0x3ac << 16) | 0x40);
hbsc              491 drivers/gpu/drm/zte/zx_plane.c 	zx_writel(hbsc + HBSC_THRESHOLD_COL2, (0x3c0 << 16) | 0x40);
hbsc              492 drivers/gpu/drm/zte/zx_plane.c 	zx_writel(hbsc + HBSC_THRESHOLD_COL3, (0x3c0 << 16) | 0x40);
hbsc               15 drivers/gpu/drm/zte/zx_plane.h 	void __iomem *hbsc;
hbsc              555 drivers/gpu/drm/zte/zx_vou.c 		zplane->hbsc = vou->osd + MAIN_HBSC_OFFSET;
hbsc              566 drivers/gpu/drm/zte/zx_vou.c 		zplane->hbsc = vou->osd + AUX_HBSC_OFFSET;
hbsc              659 drivers/gpu/drm/zte/zx_vou.c 		zplane->hbsc = vou->osd + HBSC_VL_OFFSET(i);