h_taps 430 drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h DC_LOG_BANDWIDTH_CALCS(" [bw_fixed] h_taps[%d]:%d", i, bw_fixed_to_int(data->h_taps[i])); h_taps 367 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->h_taps[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1); h_taps 368 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->h_taps[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1); h_taps 421 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->h_taps[i] = bw_int_to_fixed(1); h_taps 511 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (bw_mtn(data->hsr[i], data->h_taps[i])) { h_taps 515 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (dceip->pre_downscaler_enabled == 1 && bw_mtn(data->hsr[i], bw_int_to_fixed(1)) && bw_leq(data->hsr[i], bw_ceil2(bw_div(data->h_taps[i], bw_int_to_fixed(4)), bw_int_to_fixed(1)))) { h_taps 1247 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->scaler_limits_factor = bw_max3(bw_int_to_fixed(1), bw_ceil2(bw_div(data->h_taps[i], bw_int_to_fixed(4)), bw_int_to_fixed(1)), bw_mul(data->hsr[i], bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_int_to_fixed(1)))); h_taps 1698 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->scaler_limits_factor = bw_max3(bw_int_to_fixed(1), bw_ceil2(bw_div(data->h_taps[i], bw_int_to_fixed(4)), bw_int_to_fixed(1)), bw_mul(data->hsr[i], bw_max2(bw_div(data->v_taps[i], data->v_scaler_efficiency), bw_int_to_fixed(1)))); h_taps 2802 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); h_taps 2857 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.h_taps); h_taps 2904 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); h_taps 2955 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->h_taps[num_displays + 4] = pipe[i].stream->src.width == pipe[i].stream->dst.width ? bw_int_to_fixed(1) : bw_int_to_fixed(2); h_taps 2965 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->h_taps[num_displays + 4] = bw_int_to_fixed(1); h_taps 387 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps; h_taps 984 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps; h_taps 86 drivers/gpu/drm/amd/display/dc/core/dc_debug.c plane_state->scaling_quality.h_taps, h_taps 290 drivers/gpu/drm/amd/display/dc/core/dc_debug.c update->scaling_info->scaling_quality.h_taps, h_taps 897 drivers/gpu/drm/amd/display/dc/core/dc_resource.c dc_fixpt_add_int(data->ratios.horz, data->taps.h_taps + 1), 2), 19); h_taps 916 drivers/gpu/drm/amd/display/dc/core/dc_resource.c orthogonal_rotation ? data->taps.v_taps : data->taps.h_taps, h_taps 934 drivers/gpu/drm/amd/display/dc/core/dc_resource.c orthogonal_rotation ? data->taps.h_taps : data->taps.v_taps, h_taps 1010 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.taps.h_taps = 1; h_taps 613 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t h_taps; h_taps 122 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c if (data->taps.h_taps + data->taps.v_taps <= 2) { h_taps 132 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c SCL_H_NUM_OF_TAPS, data->taps.h_taps - 1, h_taps 267 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c dc_fixpt_from_int(data->taps.h_taps + 1)), h_taps 353 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c coeffs_h = get_filter_coeffs_16p(data->taps.h_taps, data->ratios.horz); h_taps 377 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c data->taps.h_taps, h_taps 382 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c data->taps.h_taps, h_taps 922 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c scl_data->taps.h_taps = decide_taps(scl_data->ratios.horz, in_taps->h_taps, false); h_taps 924 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c scl_data->taps.h_taps_c = decide_taps(scl_data->ratios.horz_c, in_taps->h_taps, true); h_taps 167 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c set_reg_field_value(value, data->taps.h_taps - 1, h_taps 178 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c if (data->taps.h_taps + data->taps.v_taps > 2) { h_taps 563 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c coeffs_h = get_filter_coeffs_64p(data->taps.h_taps, data->ratios.horz); h_taps 586 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c data->taps.h_taps, h_taps 169 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c if (in_taps->h_taps == 0) h_taps 170 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c scl_data->taps.h_taps = 4; h_taps 172 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c scl_data->taps.h_taps = in_taps->h_taps; h_taps 191 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c scl_data->taps.h_taps = 1; h_taps 315 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3 h_taps 317 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1); h_taps 337 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c scl_data->taps.h_taps, scl_data->ratios.horz); h_taps 358 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp, scl_data->taps.h_taps, h_taps 571 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1, h_taps 731 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1, h_taps 411 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c if (in_taps->h_taps == 0) { h_taps 413 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->taps.h_taps = 8; h_taps 415 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->taps.h_taps = 4; h_taps 417 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->taps.h_taps = in_taps->h_taps; h_taps 445 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->taps.h_taps = 1; h_taps 726 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c uint32_t h_taps_luma = num_taps.h_taps; h_taps 2124 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps; h_taps 396 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed h_taps[maximum_number_of_surfaces];