h_scale_ratio     432 drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h 		DC_LOG_BANDWIDTH_CALCS("	[bw_fixed] h_scale_ratio[%d]:%d", i, bw_fixed_to_int(data->h_scale_ratio[i]));
h_scale_ratio     394 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	data->h_scale_ratio[maximum_number_of_surfaces - 2] = bw_int_to_fixed(1);
h_scale_ratio     395 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	data->h_scale_ratio[maximum_number_of_surfaces - 1] = bw_int_to_fixed(1);
h_scale_ratio     420 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			if (bw_equ(data->h_scale_ratio[i], bw_int_to_fixed(1)) && bw_equ(data->v_scale_ratio[i], bw_int_to_fixed(1)) && surface_type[i] == bw_def_graphics && data->stereo_mode[i] == bw_def_mono && data->interlace_mode[i] == 0) {
h_scale_ratio     428 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 				data->hsr_after_surface_type = bw_div(data->h_scale_ratio[i], bw_int_to_fixed(2));
h_scale_ratio     435 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 				data->hsr_after_surface_type = data->h_scale_ratio[i];
h_scale_ratio    2804 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.horz.value);
h_scale_ratio    2859 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			data->h_scale_ratio[num_displays * 2 + j] = fixed31_32_to_bw_fixed(
h_scale_ratio    2906 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.horz.value);
h_scale_ratio    2957 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			data->h_scale_ratio[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->src.width, pipe[i].stream->dst.width);
h_scale_ratio    2967 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			data->h_scale_ratio[num_displays + 4] = bw_int_to_fixed(1);
h_scale_ratio     429 drivers/gpu/drm/amd/display/dc/dc_hw_types.h 	struct fixed31_32 h_scale_ratio;
h_scale_ratio    2692 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		.h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
h_scale_ratio    1161 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	ASSERT(param->h_scale_ratio.value);
h_scale_ratio    1163 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	if (param->h_scale_ratio.value)
h_scale_ratio    1166 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 				param->h_scale_ratio));
h_scale_ratio    2963 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		.h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
h_scale_ratio     984 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	ASSERT(param->h_scale_ratio.value);
h_scale_ratio     986 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	if (param->h_scale_ratio.value)
h_scale_ratio     989 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 				param->h_scale_ratio));
h_scale_ratio     398 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h 	struct bw_fixed h_scale_ratio[maximum_number_of_surfaces];