h_init_phase_chroma_frac  733 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	uint32_t h_init_phase_chroma_frac = 0;
h_init_phase_chroma_frac  776 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	h_init_phase_chroma_frac = (h_init_phase_chroma & 0x7ffff) << 5;
h_init_phase_chroma_frac  782 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	REG_UPDATE(WBSCL_HORZ_FILTER_INIT_CBCR, WBSCL_H_INIT_FRAC_CBCR, h_init_phase_chroma_frac);