h_back_porch      286 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	uint32_t h_back_porch;
h_back_porch      480 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		h_back_porch = h_blank - hw_crtc_timing.h_front_porch -
h_back_porch      484 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;
h_back_porch     1115 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c 	uint32_t h_back_porch, hsync_offset, h_sync_start;
h_back_porch     1154 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c 	h_back_porch = h_blank - (h_sync_start -
h_back_porch     1159 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c 	if (h_back_porch < tg110->min_h_back_porch)
h_back_porch      257 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	uint32_t h_back_porch;
h_back_porch      441 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	h_back_porch = h_blank - hw_crtc_timing.h_front_porch -
h_back_porch      445 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	h_active_start = hw_crtc_timing.h_sync_width + h_back_porch;
h_back_porch       74 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 	timing->h_back_porch = mode->htotal - mode->hsync_end;
h_back_porch      109 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 	    timing->h_back_porch + timing->h_front_porch +
h_back_porch       98 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	hsync_period = p->hsync_pulse_width + p->h_back_porch + p->width +
h_back_porch      109 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 		display_v_start += p->hsync_pulse_width + p->h_back_porch;
h_back_porch      113 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	hsync_start_x = p->h_back_porch + p->hsync_pulse_width;
h_back_porch       22 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h 	u32 h_back_porch;
h_back_porch     1180 drivers/gpu/drm/tegra/hdmi.c 	unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
h_back_porch     1201 drivers/gpu/drm/tegra/hdmi.c 	h_back_porch = mode->htotal - mode->hsync_end;
h_back_porch     1229 drivers/gpu/drm/tegra/hdmi.c 	pulse_start = 1 + h_sync_width + h_back_porch - 10;
h_back_porch     1281 drivers/gpu/drm/tegra/hdmi.c 	value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
h_back_porch       49 drivers/video/fbdev/core/fbcvt.c 	u32 h_back_porch;
h_back_porch      275 drivers/video/fbdev/core/fbcvt.c 	mode->left_margin = cvt->h_back_porch;
h_back_porch      369 drivers/video/fbdev/core/fbcvt.c 	cvt.h_back_porch = cvt.hblank/2 + cvt.h_margin;
h_back_porch      370 drivers/video/fbdev/core/fbcvt.c 	cvt.h_front_porch = cvt.hblank - cvt.hsync - cvt.h_back_porch +