h_addressable 3144 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c dst.width = stream->timing.h_addressable; h_addressable 3164 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c dst.x = (stream->timing.h_addressable - dst.width) / 2; h_addressable 3365 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c timing_out->h_addressable = mode_in->crtc_hdisplay; h_addressable 1753 drivers/gpu/drm/amd/display/dc/bios/command_table.c params.usH_Disp = cpu_to_le16((uint16_t)(bp_params->h_addressable)); h_addressable 1826 drivers/gpu/drm/amd/display/dc/bios/command_table.c params.usH_Size = cpu_to_le16((uint16_t)bp_params->h_addressable); h_addressable 1829 drivers/gpu/drm/amd/display/dc/bios/command_table.c cpu_to_le16((uint16_t)(bp_params->h_total - bp_params->h_addressable)); h_addressable 1839 drivers/gpu/drm/amd/display/dc/bios/command_table.c cpu_to_le16((uint16_t)(bp_params->h_sync_start - bp_params->h_addressable)); h_addressable 382 drivers/gpu/drm/amd/display/dc/bios/command_table2.c params.h_size = cpu_to_le16((uint16_t)bp_params->h_addressable); h_addressable 386 drivers/gpu/drm/amd/display/dc/bios/command_table2.c bp_params->h_addressable)); h_addressable 399 drivers/gpu/drm/amd/display/dc/bios/command_table2.c bp_params->h_addressable)); h_addressable 2962 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_addressable); h_addressable 423 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c - pipe->stream->timing.h_addressable h_addressable 892 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->viewport_width[input_idx] = pipe->stream->timing.h_addressable; h_addressable 362 drivers/gpu/drm/amd/display/dc/core/dc.c param.windowa_x_end = pipe->stream->timing.h_addressable; h_addressable 366 drivers/gpu/drm/amd/display/dc/core/dc.c param.windowb_x_end = pipe->stream->timing.h_addressable; h_addressable 1136 drivers/gpu/drm/amd/display/dc/core/dc.c context->streams[i]->timing.h_addressable, h_addressable 2035 drivers/gpu/drm/amd/display/dc/core/dc_link.c bool is_vga_mode = (stream->timing.h_addressable == 640) h_addressable 1875 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c timing->h_addressable == (uint32_t) 640 && h_addressable 3059 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c int width = pipe_ctx->stream->timing.h_addressable + h_addressable 399 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; h_addressable 500 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; h_addressable 384 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (stream1->timing.h_addressable h_addressable 385 drivers/gpu/drm/amd/display/dc/core/dc_resource.c != stream2->timing.h_addressable) h_addressable 993 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right; h_addressable 779 drivers/gpu/drm/amd/display/dc/dc_hw_types.h uint32_t h_addressable; h_addressable 478 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right; h_addressable 514 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right, h_addressable 674 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c timing->h_addressable h_addressable 1132 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c stream->timing.h_addressable h_addressable 1866 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c params.source_view_width = pipe_ctx->stream->timing.h_addressable; h_addressable 913 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c context->streams[0]->timing.h_addressable, h_addressable 296 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t h_sync_start = dc_crtc_timing->h_addressable + hsync_offset; h_addressable 311 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c bp_params.h_addressable = h_addressable 312 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c patched_crtc_timing.h_addressable; h_addressable 606 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c uint32_t h_sync_start = timing->h_addressable + hsync_offset; h_addressable 665 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c tmp = tmp + timing->h_addressable + h_addressable 1125 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c h_sync_start = timing->h_addressable + hsync_offset; h_addressable 1144 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c h_blank = (timing->h_total - timing->h_addressable - h_addressable 1155 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c timing->h_addressable - h_addressable 252 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c uint32_t h_sync_start = timing->h_addressable + hsync_offset; h_addressable 289 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c tmp = tmp + timing->h_addressable + h_addressable 440 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c uint32_t h_sync_start = timing->h_addressable + hsync_offset; h_addressable 468 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c tmp2 = tmp1 + timing->h_addressable + h_addressable 308 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c uint32_t active_width = timing->h_addressable - timing->h_border_right - timing->h_border_right; h_addressable 187 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c patched_crtc_timing.h_addressable - h_addressable 518 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c h_blank = (timing->h_total - timing->h_addressable - h_addressable 1245 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c hw_crtc_timing.h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end); h_addressable 1260 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c if (otg_timing->h_addressable != hw_crtc_timing.h_addressable) h_addressable 439 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right; h_addressable 471 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right, h_addressable 860 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; h_addressable 1948 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c timing->h_addressable h_addressable 236 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right) h_addressable 1925 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c - timing->h_addressable h_addressable 1935 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable; h_addressable 2048 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable; h_addressable 2272 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left h_addressable 532 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right; h_addressable 164 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t h_addressable;