guc 20 drivers/gpu/drm/i915/gt/intel_gt.h static inline struct intel_gt *guc_to_gt(struct intel_guc *guc) guc 22 drivers/gpu/drm/i915/gt/intel_gt.h return container_of(guc, struct intel_gt, uc.guc); guc 15 drivers/gpu/drm/i915/gt/intel_gt_irq.c static void guc_irq_handler(struct intel_guc *guc, u16 iir) guc 18 drivers/gpu/drm/i915/gt/intel_gt_irq.c intel_guc_to_host_event_handler(guc); guc 77 drivers/gpu/drm/i915/gt/intel_gt_irq.c return guc_irq_handler(>->uc.guc, iir); guc 340 drivers/gpu/drm/i915/gt/intel_gt_irq.c guc_irq_handler(>->uc.guc, gt_iir[2] >> 16); guc 1047 drivers/gpu/drm/i915/gt/intel_reset.c if (!engine->gt->uc.guc.execbuf_client) guc 1050 drivers/gpu/drm/i915/gt/intel_reset.c ret = intel_guc_reset_engine(&engine->gt->uc.guc, engine); guc 1054 drivers/gpu/drm/i915/gt/intel_reset.c engine->gt->uc.guc.execbuf_client ? "GuC " : "", guc 12 drivers/gpu/drm/i915/gt/uc/intel_guc.c static void gen8_guc_raise_irq(struct intel_guc *guc) guc 14 drivers/gpu/drm/i915/gt/uc/intel_guc.c struct intel_gt *gt = guc_to_gt(guc); guc 19 drivers/gpu/drm/i915/gt/uc/intel_guc.c static void gen11_guc_raise_irq(struct intel_guc *guc) guc 21 drivers/gpu/drm/i915/gt/uc/intel_guc.c struct intel_gt *gt = guc_to_gt(guc); guc 26 drivers/gpu/drm/i915/gt/uc/intel_guc.c static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i) guc 28 drivers/gpu/drm/i915/gt/uc/intel_guc.c GEM_BUG_ON(!guc->send_regs.base); guc 29 drivers/gpu/drm/i915/gt/uc/intel_guc.c GEM_BUG_ON(!guc->send_regs.count); guc 30 drivers/gpu/drm/i915/gt/uc/intel_guc.c GEM_BUG_ON(i >= guc->send_regs.count); guc 32 drivers/gpu/drm/i915/gt/uc/intel_guc.c return _MMIO(guc->send_regs.base + 4 * i); guc 35 drivers/gpu/drm/i915/gt/uc/intel_guc.c void intel_guc_init_send_regs(struct intel_guc *guc) guc 37 drivers/gpu/drm/i915/gt/uc/intel_guc.c struct intel_gt *gt = guc_to_gt(guc); guc 42 drivers/gpu/drm/i915/gt/uc/intel_guc.c guc->send_regs.base = guc 44 drivers/gpu/drm/i915/gt/uc/intel_guc.c guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT; guc 46 drivers/gpu/drm/i915/gt/uc/intel_guc.c guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0)); guc 47 drivers/gpu/drm/i915/gt/uc/intel_guc.c guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN; guc 51 drivers/gpu/drm/i915/gt/uc/intel_guc.c for (i = 0; i < guc->send_regs.count; i++) { guc 53 drivers/gpu/drm/i915/gt/uc/intel_guc.c guc_send_reg(guc, i), guc 56 drivers/gpu/drm/i915/gt/uc/intel_guc.c guc->send_regs.fw_domains = fw_domains; guc 59 drivers/gpu/drm/i915/gt/uc/intel_guc.c void intel_guc_init_early(struct intel_guc *guc) guc 61 drivers/gpu/drm/i915/gt/uc/intel_guc.c struct drm_i915_private *i915 = guc_to_gt(guc)->i915; guc 63 drivers/gpu/drm/i915/gt/uc/intel_guc.c intel_guc_fw_init_early(guc); guc 64 drivers/gpu/drm/i915/gt/uc/intel_guc.c intel_guc_ct_init_early(&guc->ct); guc 65 drivers/gpu/drm/i915/gt/uc/intel_guc.c intel_guc_log_init_early(&guc->log); guc 66 drivers/gpu/drm/i915/gt/uc/intel_guc.c intel_guc_submission_init_early(guc); guc 68 drivers/gpu/drm/i915/gt/uc/intel_guc.c mutex_init(&guc->send_mutex); guc 69 drivers/gpu/drm/i915/gt/uc/intel_guc.c spin_lock_init(&guc->irq_lock); guc 70 drivers/gpu/drm/i915/gt/uc/intel_guc.c guc->send = intel_guc_send_nop; guc 71 drivers/gpu/drm/i915/gt/uc/intel_guc.c guc->handler = intel_guc_to_host_event_handler_nop; guc 73 drivers/gpu/drm/i915/gt/uc/intel_guc.c guc->notify = gen11_guc_raise_irq; guc 74 drivers/gpu/drm/i915/gt/uc/intel_guc.c guc->interrupts.reset = gen11_reset_guc_interrupts; guc 75 drivers/gpu/drm/i915/gt/uc/intel_guc.c guc->interrupts.enable = gen11_enable_guc_interrupts; guc 76 drivers/gpu/drm/i915/gt/uc/intel_guc.c guc->interrupts.disable = gen11_disable_guc_interrupts; guc 78 drivers/gpu/drm/i915/gt/uc/intel_guc.c guc->notify = gen8_guc_raise_irq; guc 79 drivers/gpu/drm/i915/gt/uc/intel_guc.c guc->interrupts.reset = gen9_reset_guc_interrupts; guc 80 drivers/gpu/drm/i915/gt/uc/intel_guc.c guc->interrupts.enable = gen9_enable_guc_interrupts; guc 81 drivers/gpu/drm/i915/gt/uc/intel_guc.c guc->interrupts.disable = gen9_disable_guc_interrupts; guc 85 drivers/gpu/drm/i915/gt/uc/intel_guc.c static int guc_shared_data_create(struct intel_guc *guc) guc 90 drivers/gpu/drm/i915/gt/uc/intel_guc.c vma = intel_guc_allocate_vma(guc, PAGE_SIZE); guc 100 drivers/gpu/drm/i915/gt/uc/intel_guc.c guc->shared_data = vma; guc 101 drivers/gpu/drm/i915/gt/uc/intel_guc.c guc->shared_data_vaddr = vaddr; guc 106 drivers/gpu/drm/i915/gt/uc/intel_guc.c static void guc_shared_data_destroy(struct intel_guc *guc) guc 108 drivers/gpu/drm/i915/gt/uc/intel_guc.c i915_vma_unpin_and_release(&guc->shared_data, I915_VMA_RELEASE_MAP); guc 111 drivers/gpu/drm/i915/gt/uc/intel_guc.c static u32 guc_ctl_debug_flags(struct intel_guc *guc) guc 113 drivers/gpu/drm/i915/gt/uc/intel_guc.c u32 level = intel_guc_log_get_level(&guc->log); guc 125 drivers/gpu/drm/i915/gt/uc/intel_guc.c static u32 guc_ctl_feature_flags(struct intel_guc *guc) guc 129 drivers/gpu/drm/i915/gt/uc/intel_guc.c if (!intel_guc_is_submission_supported(guc)) guc 135 drivers/gpu/drm/i915/gt/uc/intel_guc.c static u32 guc_ctl_ctxinfo_flags(struct intel_guc *guc) guc 139 drivers/gpu/drm/i915/gt/uc/intel_guc.c if (intel_guc_is_submission_supported(guc)) { guc 142 drivers/gpu/drm/i915/gt/uc/intel_guc.c base = intel_guc_ggtt_offset(guc, guc->stage_desc_pool); guc 152 drivers/gpu/drm/i915/gt/uc/intel_guc.c static u32 guc_ctl_log_params_flags(struct intel_guc *guc) guc 154 drivers/gpu/drm/i915/gt/uc/intel_guc.c u32 offset = intel_guc_ggtt_offset(guc, guc->log.vma) >> PAGE_SHIFT; guc 193 drivers/gpu/drm/i915/gt/uc/intel_guc.c static u32 guc_ctl_ads_flags(struct intel_guc *guc) guc 195 drivers/gpu/drm/i915/gt/uc/intel_guc.c u32 ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT; guc 206 drivers/gpu/drm/i915/gt/uc/intel_guc.c static void guc_init_params(struct intel_guc *guc) guc 208 drivers/gpu/drm/i915/gt/uc/intel_guc.c u32 *params = guc->params; guc 211 drivers/gpu/drm/i915/gt/uc/intel_guc.c BUILD_BUG_ON(sizeof(guc->params) != GUC_CTL_MAX_DWORDS * sizeof(u32)); guc 213 drivers/gpu/drm/i915/gt/uc/intel_guc.c params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc); guc 214 drivers/gpu/drm/i915/gt/uc/intel_guc.c params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); guc 215 drivers/gpu/drm/i915/gt/uc/intel_guc.c params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc); guc 216 drivers/gpu/drm/i915/gt/uc/intel_guc.c params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc); guc 217 drivers/gpu/drm/i915/gt/uc/intel_guc.c params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc); guc 228 drivers/gpu/drm/i915/gt/uc/intel_guc.c void intel_guc_write_params(struct intel_guc *guc) guc 230 drivers/gpu/drm/i915/gt/uc/intel_guc.c struct intel_uncore *uncore = guc_to_gt(guc)->uncore; guc 243 drivers/gpu/drm/i915/gt/uc/intel_guc.c intel_uncore_write(uncore, SOFT_SCRATCH(1 + i), guc->params[i]); guc 248 drivers/gpu/drm/i915/gt/uc/intel_guc.c int intel_guc_init(struct intel_guc *guc) guc 250 drivers/gpu/drm/i915/gt/uc/intel_guc.c struct intel_gt *gt = guc_to_gt(guc); guc 253 drivers/gpu/drm/i915/gt/uc/intel_guc.c ret = intel_uc_fw_init(&guc->fw); guc 257 drivers/gpu/drm/i915/gt/uc/intel_guc.c ret = guc_shared_data_create(guc); guc 260 drivers/gpu/drm/i915/gt/uc/intel_guc.c GEM_BUG_ON(!guc->shared_data); guc 262 drivers/gpu/drm/i915/gt/uc/intel_guc.c ret = intel_guc_log_create(&guc->log); guc 266 drivers/gpu/drm/i915/gt/uc/intel_guc.c ret = intel_guc_ads_create(guc); guc 269 drivers/gpu/drm/i915/gt/uc/intel_guc.c GEM_BUG_ON(!guc->ads_vma); guc 271 drivers/gpu/drm/i915/gt/uc/intel_guc.c ret = intel_guc_ct_init(&guc->ct); guc 275 drivers/gpu/drm/i915/gt/uc/intel_guc.c if (intel_guc_is_submission_supported(guc)) { guc 280 drivers/gpu/drm/i915/gt/uc/intel_guc.c ret = intel_guc_submission_init(guc); guc 286 drivers/gpu/drm/i915/gt/uc/intel_guc.c guc_init_params(guc); guc 294 drivers/gpu/drm/i915/gt/uc/intel_guc.c intel_guc_ct_fini(&guc->ct); guc 296 drivers/gpu/drm/i915/gt/uc/intel_guc.c intel_guc_ads_destroy(guc); guc 298 drivers/gpu/drm/i915/gt/uc/intel_guc.c intel_guc_log_destroy(&guc->log); guc 300 drivers/gpu/drm/i915/gt/uc/intel_guc.c guc_shared_data_destroy(guc); guc 302 drivers/gpu/drm/i915/gt/uc/intel_guc.c intel_uc_fw_fini(&guc->fw); guc 304 drivers/gpu/drm/i915/gt/uc/intel_guc.c intel_uc_fw_cleanup_fetch(&guc->fw); guc 309 drivers/gpu/drm/i915/gt/uc/intel_guc.c void intel_guc_fini(struct intel_guc *guc) guc 311 drivers/gpu/drm/i915/gt/uc/intel_guc.c struct intel_gt *gt = guc_to_gt(guc); guc 313 drivers/gpu/drm/i915/gt/uc/intel_guc.c if (!intel_uc_fw_is_available(&guc->fw)) guc 318 drivers/gpu/drm/i915/gt/uc/intel_guc.c if (intel_guc_is_submission_supported(guc)) guc 319 drivers/gpu/drm/i915/gt/uc/intel_guc.c intel_guc_submission_fini(guc); guc 321 drivers/gpu/drm/i915/gt/uc/intel_guc.c intel_guc_ct_fini(&guc->ct); guc 323 drivers/gpu/drm/i915/gt/uc/intel_guc.c intel_guc_ads_destroy(guc); guc 324 drivers/gpu/drm/i915/gt/uc/intel_guc.c intel_guc_log_destroy(&guc->log); guc 325 drivers/gpu/drm/i915/gt/uc/intel_guc.c guc_shared_data_destroy(guc); guc 326 drivers/gpu/drm/i915/gt/uc/intel_guc.c intel_uc_fw_fini(&guc->fw); guc 327 drivers/gpu/drm/i915/gt/uc/intel_guc.c intel_uc_fw_cleanup_fetch(&guc->fw); guc 330 drivers/gpu/drm/i915/gt/uc/intel_guc.c int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len, guc 337 drivers/gpu/drm/i915/gt/uc/intel_guc.c void intel_guc_to_host_event_handler_nop(struct intel_guc *guc) guc 345 drivers/gpu/drm/i915/gt/uc/intel_guc.c int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, guc 348 drivers/gpu/drm/i915/gt/uc/intel_guc.c struct intel_uncore *uncore = guc_to_gt(guc)->uncore; guc 354 drivers/gpu/drm/i915/gt/uc/intel_guc.c GEM_BUG_ON(len > guc->send_regs.count); guc 363 drivers/gpu/drm/i915/gt/uc/intel_guc.c mutex_lock(&guc->send_mutex); guc 364 drivers/gpu/drm/i915/gt/uc/intel_guc.c intel_uncore_forcewake_get(uncore, guc->send_regs.fw_domains); guc 367 drivers/gpu/drm/i915/gt/uc/intel_guc.c intel_uncore_write(uncore, guc_send_reg(guc, i), action[i]); guc 369 drivers/gpu/drm/i915/gt/uc/intel_guc.c intel_uncore_posting_read(uncore, guc_send_reg(guc, i - 1)); guc 371 drivers/gpu/drm/i915/gt/uc/intel_guc.c intel_guc_notify(guc); guc 378 drivers/gpu/drm/i915/gt/uc/intel_guc.c guc_send_reg(guc, 0), guc 394 drivers/gpu/drm/i915/gt/uc/intel_guc.c int count = min(response_buf_size, guc->send_regs.count - 1); guc 398 drivers/gpu/drm/i915/gt/uc/intel_guc.c guc_send_reg(guc, i + 1)); guc 405 drivers/gpu/drm/i915/gt/uc/intel_guc.c intel_uncore_forcewake_put(uncore, guc->send_regs.fw_domains); guc 406 drivers/gpu/drm/i915/gt/uc/intel_guc.c mutex_unlock(&guc->send_mutex); guc 411 drivers/gpu/drm/i915/gt/uc/intel_guc.c int intel_guc_to_host_process_recv_msg(struct intel_guc *guc, guc 420 drivers/gpu/drm/i915/gt/uc/intel_guc.c msg = payload[0] & guc->msg_enabled_mask; guc 424 drivers/gpu/drm/i915/gt/uc/intel_guc.c intel_guc_log_handle_flush_event(&guc->log); guc 429 drivers/gpu/drm/i915/gt/uc/intel_guc.c int intel_guc_sample_forcewake(struct intel_guc *guc) guc 431 drivers/gpu/drm/i915/gt/uc/intel_guc.c struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915; guc 442 drivers/gpu/drm/i915/gt/uc/intel_guc.c return intel_guc_send(guc, action, ARRAY_SIZE(action)); guc 456 drivers/gpu/drm/i915/gt/uc/intel_guc.c int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset) guc 463 drivers/gpu/drm/i915/gt/uc/intel_guc.c return intel_guc_send(guc, action, ARRAY_SIZE(action)); guc 470 drivers/gpu/drm/i915/gt/uc/intel_guc.c int intel_guc_suspend(struct intel_guc *guc) guc 472 drivers/gpu/drm/i915/gt/uc/intel_guc.c struct intel_uncore *uncore = guc_to_gt(guc)->uncore; guc 493 drivers/gpu/drm/i915/gt/uc/intel_guc.c ret = intel_guc_send(guc, action, ARRAY_SIZE(action)); guc 518 drivers/gpu/drm/i915/gt/uc/intel_guc.c int intel_guc_reset_engine(struct intel_guc *guc, guc 523 drivers/gpu/drm/i915/gt/uc/intel_guc.c GEM_BUG_ON(!guc->execbuf_client); guc 530 drivers/gpu/drm/i915/gt/uc/intel_guc.c data[5] = guc->execbuf_client->stage_id; guc 531 drivers/gpu/drm/i915/gt/uc/intel_guc.c data[6] = intel_guc_ggtt_offset(guc, guc->shared_data); guc 533 drivers/gpu/drm/i915/gt/uc/intel_guc.c return intel_guc_send(guc, data, ARRAY_SIZE(data)); guc 540 drivers/gpu/drm/i915/gt/uc/intel_guc.c int intel_guc_resume(struct intel_guc *guc) guc 547 drivers/gpu/drm/i915/gt/uc/intel_guc.c return intel_guc_send(guc, action, ARRAY_SIZE(action)); guc 591 drivers/gpu/drm/i915/gt/uc/intel_guc.c struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size) guc 593 drivers/gpu/drm/i915/gt/uc/intel_guc.c struct intel_gt *gt = guc_to_gt(guc); guc 37 drivers/gpu/drm/i915/gt/uc/intel_guc.h void (*reset)(struct intel_guc *guc); guc 38 drivers/gpu/drm/i915/gt/uc/intel_guc.h void (*enable)(struct intel_guc *guc); guc 39 drivers/gpu/drm/i915/gt/uc/intel_guc.h void (*disable)(struct intel_guc *guc); guc 76 drivers/gpu/drm/i915/gt/uc/intel_guc.h int (*send)(struct intel_guc *guc, const u32 *data, u32 len, guc 80 drivers/gpu/drm/i915/gt/uc/intel_guc.h void (*handler)(struct intel_guc *guc); guc 83 drivers/gpu/drm/i915/gt/uc/intel_guc.h void (*notify)(struct intel_guc *guc); guc 87 drivers/gpu/drm/i915/gt/uc/intel_guc.h inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len) guc 89 drivers/gpu/drm/i915/gt/uc/intel_guc.h return guc->send(guc, action, len, NULL, 0); guc 93 drivers/gpu/drm/i915/gt/uc/intel_guc.h intel_guc_send_and_receive(struct intel_guc *guc, const u32 *action, u32 len, guc 96 drivers/gpu/drm/i915/gt/uc/intel_guc.h return guc->send(guc, action, len, response_buf, response_buf_size); guc 99 drivers/gpu/drm/i915/gt/uc/intel_guc.h static inline void intel_guc_notify(struct intel_guc *guc) guc 101 drivers/gpu/drm/i915/gt/uc/intel_guc.h guc->notify(guc); guc 104 drivers/gpu/drm/i915/gt/uc/intel_guc.h static inline void intel_guc_to_host_event_handler(struct intel_guc *guc) guc 106 drivers/gpu/drm/i915/gt/uc/intel_guc.h guc->handler(guc); guc 125 drivers/gpu/drm/i915/gt/uc/intel_guc.h static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc, guc 136 drivers/gpu/drm/i915/gt/uc/intel_guc.h void intel_guc_init_early(struct intel_guc *guc); guc 137 drivers/gpu/drm/i915/gt/uc/intel_guc.h void intel_guc_init_send_regs(struct intel_guc *guc); guc 138 drivers/gpu/drm/i915/gt/uc/intel_guc.h void intel_guc_write_params(struct intel_guc *guc); guc 139 drivers/gpu/drm/i915/gt/uc/intel_guc.h int intel_guc_init(struct intel_guc *guc); guc 140 drivers/gpu/drm/i915/gt/uc/intel_guc.h void intel_guc_fini(struct intel_guc *guc); guc 141 drivers/gpu/drm/i915/gt/uc/intel_guc.h int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len, guc 143 drivers/gpu/drm/i915/gt/uc/intel_guc.h int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, guc 145 drivers/gpu/drm/i915/gt/uc/intel_guc.h void intel_guc_to_host_event_handler(struct intel_guc *guc); guc 146 drivers/gpu/drm/i915/gt/uc/intel_guc.h void intel_guc_to_host_event_handler_nop(struct intel_guc *guc); guc 147 drivers/gpu/drm/i915/gt/uc/intel_guc.h int intel_guc_to_host_process_recv_msg(struct intel_guc *guc, guc 149 drivers/gpu/drm/i915/gt/uc/intel_guc.h int intel_guc_sample_forcewake(struct intel_guc *guc); guc 150 drivers/gpu/drm/i915/gt/uc/intel_guc.h int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset); guc 151 drivers/gpu/drm/i915/gt/uc/intel_guc.h int intel_guc_suspend(struct intel_guc *guc); guc 152 drivers/gpu/drm/i915/gt/uc/intel_guc.h int intel_guc_resume(struct intel_guc *guc); guc 153 drivers/gpu/drm/i915/gt/uc/intel_guc.h struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size); guc 155 drivers/gpu/drm/i915/gt/uc/intel_guc.h static inline bool intel_guc_is_supported(struct intel_guc *guc) guc 157 drivers/gpu/drm/i915/gt/uc/intel_guc.h return intel_uc_fw_is_supported(&guc->fw); guc 160 drivers/gpu/drm/i915/gt/uc/intel_guc.h static inline bool intel_guc_is_enabled(struct intel_guc *guc) guc 162 drivers/gpu/drm/i915/gt/uc/intel_guc.h return intel_uc_fw_is_enabled(&guc->fw); guc 165 drivers/gpu/drm/i915/gt/uc/intel_guc.h static inline bool intel_guc_is_running(struct intel_guc *guc) guc 167 drivers/gpu/drm/i915/gt/uc/intel_guc.h return intel_uc_fw_is_running(&guc->fw); guc 170 drivers/gpu/drm/i915/gt/uc/intel_guc.h static inline int intel_guc_sanitize(struct intel_guc *guc) guc 172 drivers/gpu/drm/i915/gt/uc/intel_guc.h intel_uc_fw_sanitize(&guc->fw); guc 173 drivers/gpu/drm/i915/gt/uc/intel_guc.h guc->mmio_msg = 0; guc 178 drivers/gpu/drm/i915/gt/uc/intel_guc.h static inline bool intel_guc_is_submission_supported(struct intel_guc *guc) guc 180 drivers/gpu/drm/i915/gt/uc/intel_guc.h return guc->submission_supported; guc 183 drivers/gpu/drm/i915/gt/uc/intel_guc.h static inline void intel_guc_enable_msg(struct intel_guc *guc, u32 mask) guc 185 drivers/gpu/drm/i915/gt/uc/intel_guc.h spin_lock_irq(&guc->irq_lock); guc 186 drivers/gpu/drm/i915/gt/uc/intel_guc.h guc->msg_enabled_mask |= mask; guc 187 drivers/gpu/drm/i915/gt/uc/intel_guc.h spin_unlock_irq(&guc->irq_lock); guc 190 drivers/gpu/drm/i915/gt/uc/intel_guc.h static inline void intel_guc_disable_msg(struct intel_guc *guc, u32 mask) guc 192 drivers/gpu/drm/i915/gt/uc/intel_guc.h spin_lock_irq(&guc->irq_lock); guc 193 drivers/gpu/drm/i915/gt/uc/intel_guc.h guc->msg_enabled_mask &= ~mask; guc 194 drivers/gpu/drm/i915/gt/uc/intel_guc.h spin_unlock_irq(&guc->irq_lock); guc 197 drivers/gpu/drm/i915/gt/uc/intel_guc.h int intel_guc_reset_engine(struct intel_guc *guc, guc 68 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c static void __guc_ads_init(struct intel_guc *guc) guc 70 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915; guc 71 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c struct __guc_ads_blob *blob = guc->ads_blob; guc 109 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c base = intel_guc_ggtt_offset(guc, guc->ads_vma); guc 125 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c i915_gem_object_flush_map(guc->ads_vma->obj); guc 135 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c int intel_guc_ads_create(struct intel_guc *guc) guc 142 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c GEM_BUG_ON(guc->ads_vma); guc 144 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c vma = intel_guc_allocate_vma(guc, size); guc 154 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c guc->ads_vma = vma; guc 155 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c guc->ads_blob = blob; guc 157 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c __guc_ads_init(guc); guc 162 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c i915_vma_unpin_and_release(&guc->ads_vma, 0); guc 166 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c void intel_guc_ads_destroy(struct intel_guc *guc) guc 168 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c i915_vma_unpin_and_release(&guc->ads_vma, I915_VMA_RELEASE_MAP); guc 179 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c void intel_guc_ads_reset(struct intel_guc *guc) guc 181 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c if (!guc->ads_vma) guc 183 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c __guc_ads_init(guc); guc 11 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h int intel_guc_ads_create(struct intel_guc *guc); guc 12 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h void intel_guc_ads_destroy(struct intel_guc *guc); guc 13 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h void intel_guc_ads_reset(struct intel_guc *guc); guc 86 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c static int guc_action_register_ct_buffer(struct intel_guc *guc, guc 99 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c err = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0); guc 106 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c static int guc_action_deregister_ct_buffer(struct intel_guc *guc, guc 118 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c err = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0); guc 125 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c static int ctch_init(struct intel_guc *guc, guc 158 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c vma = intel_guc_allocate_vma(guc, PAGE_SIZE); guc 172 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c intel_guc_ggtt_offset(guc, ctch->vma)); guc 191 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c static void ctch_fini(struct intel_guc *guc, guc 199 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c static int ctch_enable(struct intel_guc *guc, guc 211 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c base = intel_guc_ggtt_offset(guc, ctch->vma); guc 227 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c err = guc_action_register_ct_buffer(guc, guc 233 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c err = guc_action_register_ct_buffer(guc, guc 244 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c guc_action_deregister_ct_buffer(guc, guc 252 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c static void ctch_disable(struct intel_guc *guc, guc 259 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c guc_action_deregister_ct_buffer(guc, guc 262 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c guc_action_deregister_ct_buffer(guc, guc 514 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len, guc 517 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c struct intel_guc_ct *ct = &guc->ct; guc 522 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c mutex_lock(&guc->send_mutex); guc 534 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c mutex_unlock(&guc->send_mutex); guc 685 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c struct intel_guc *guc = ct_to_guc(ct); guc 692 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c ret = intel_guc_to_host_process_recv_msg(guc, payload, len); guc 819 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c void intel_guc_to_host_event_handler_ct(struct intel_guc *guc) guc 821 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c struct intel_guc_ct *ct = &guc->ct; guc 837 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c struct intel_guc *guc = ct_to_guc(ct); guc 841 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c err = ctch_init(guc, ctch); guc 861 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c struct intel_guc *guc = ct_to_guc(ct); guc 864 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c ctch_fini(guc, ctch); guc 875 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c struct intel_guc *guc = ct_to_guc(ct); guc 881 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c return ctch_enable(guc, ctch); guc 890 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c struct intel_guc *guc = ct_to_guc(ct); guc 896 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c ctch_disable(guc, ctch); guc 89 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len, guc 91 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h void intel_guc_to_host_event_handler_ct(struct intel_guc *guc); guc 22 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c void intel_guc_fw_init_early(struct intel_guc *guc) guc 24 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c struct drm_i915_private *i915 = guc_to_gt(guc)->i915; guc 26 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c intel_uc_fw_init_early(&guc->fw, INTEL_UC_FW_TYPE_GUC, HAS_GT_UC(i915), guc 133 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c int intel_guc_fw_upload(struct intel_guc *guc) guc 135 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c struct intel_gt *gt = guc_to_gt(guc); guc 146 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c guc_xfer_rsa(&guc->fw, uncore); guc 152 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c ret = intel_uc_fw_upload(&guc->fw, gt, 0x2000, UOS_MOVE); guc 160 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_RUNNING); guc 164 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_FAIL); guc 11 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.h void intel_guc_fw_init_early(struct intel_guc *guc); guc 12 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.h int intel_guc_fw_upload(struct intel_guc *guc); guc 24 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c static int guc_action_flush_log_complete(struct intel_guc *guc) guc 30 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c return intel_guc_send(guc, action, ARRAY_SIZE(action)); guc 33 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c static int guc_action_flush_log(struct intel_guc *guc) guc 40 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c return intel_guc_send(guc, action, ARRAY_SIZE(action)); guc 43 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c static int guc_action_control_log(struct intel_guc *guc, bool enable, guc 55 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c return intel_guc_send(guc, action, ARRAY_SIZE(action)); guc 368 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c struct intel_guc *guc = log_to_guc(log); guc 369 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915; guc 415 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c struct intel_guc *guc = log_to_guc(log); guc 416 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915; guc 426 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c guc_action_flush_log_complete(guc); guc 454 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c struct intel_guc *guc = log_to_guc(log); guc 483 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c vma = intel_guc_allocate_vma(guc, guc_log_size); guc 511 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c struct intel_guc *guc = log_to_guc(log); guc 512 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915; guc 532 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c ret = guc_action_control_log(guc, guc 609 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c struct intel_guc *guc = log_to_guc(log); guc 610 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c struct drm_i915_private *i915 = guc_to_gt(guc)->i915; guc 620 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c guc_action_flush_log(guc); guc 628 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c struct intel_guc *guc = log_to_guc(log); guc 629 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c struct drm_i915_private *i915 = guc_to_gt(guc)->i915; guc 106 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c id = find_next_zero_bit(client->guc->doorbell_bitmap, end, offset); guc 110 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c __set_bit(id, client->guc->doorbell_bitmap); guc 123 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c return test_bit(client->doorbell_id, client->guc->doorbell_bitmap); guc 130 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c __clear_bit(client->doorbell_id, client->guc->doorbell_bitmap); guc 138 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c static int __guc_allocate_doorbell(struct intel_guc *guc, u32 stage_id) guc 145 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c return intel_guc_send(guc, action, ARRAY_SIZE(action)); guc 148 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c static int __guc_deallocate_doorbell(struct intel_guc *guc, u32 stage_id) guc 155 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c return intel_guc_send(guc, action, ARRAY_SIZE(action)); guc 160 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c struct guc_stage_desc *base = client->guc->stage_desc_pool_vaddr; guc 186 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c static bool __doorbell_valid(struct intel_guc *guc, u16 db_id) guc 188 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c struct intel_uncore *uncore = guc_to_gt(guc)->uncore; guc 215 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c if (wait_for_us(!__doorbell_valid(client->guc, db_id), 10)) guc 229 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c ret = __guc_allocate_doorbell(client->guc, client->stage_id); guc 248 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c ret = __guc_deallocate_doorbell(client->guc, client->stage_id); guc 258 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c static unsigned long __select_cacheline(struct intel_guc *guc) guc 263 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c offset = offset_in_page(guc->db_cacheline); guc 266 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c guc->db_cacheline += cache_line_size(); guc 269 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c offset, guc->db_cacheline, cache_line_size()); guc 311 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c static int guc_stage_desc_pool_create(struct intel_guc *guc) guc 316 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c vma = intel_guc_allocate_vma(guc, guc 328 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c guc->stage_desc_pool = vma; guc 329 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c guc->stage_desc_pool_vaddr = vaddr; guc 330 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c ida_init(&guc->stage_ids); guc 335 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c static void guc_stage_desc_pool_destroy(struct intel_guc *guc) guc 337 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c ida_destroy(&guc->stage_ids); guc 338 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c i915_vma_unpin_and_release(&guc->stage_desc_pool, I915_VMA_RELEASE_MAP); guc 350 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c struct intel_guc *guc = client->guc; guc 369 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c gfx_addr = intel_guc_ggtt_offset(guc, client->vma); guc 463 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c static void guc_add_request(struct intel_guc *guc, struct i915_request *rq) guc 465 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c struct intel_guc_client *client = guc->execbuf_client; guc 494 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c struct intel_guc *guc = &engine->gt->uc.guc; guc 495 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c struct intel_guc_client *client = guc->execbuf_client; guc 503 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c guc_add_request(guc, rq); guc 758 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c static bool doorbell_ok(struct intel_guc *guc, u16 db_id) guc 764 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c valid = __doorbell_valid(guc, db_id); guc 766 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c if (test_bit(db_id, guc->doorbell_bitmap) == valid) guc 775 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c static bool guc_verify_doorbells(struct intel_guc *guc) guc 781 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c if (!doorbell_ok(guc, db_id)) guc 798 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c guc_client_alloc(struct intel_guc *guc, u32 priority) guc 809 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c client->guc = guc; guc 814 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c ret = ida_simple_get(&guc->stage_ids, 0, GUC_MAX_STAGE_DESCRIPTORS, guc 822 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c vma = intel_guc_allocate_vma(guc, GUC_DB_SIZE + GUC_WQ_SIZE); guc 842 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c client->doorbell_offset = __select_cacheline(guc); guc 866 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c ida_simple_remove(&guc->stage_ids, client->stage_id); guc 876 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c ida_simple_remove(&client->guc->stage_ids, client->stage_id); guc 893 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c static int guc_clients_create(struct intel_guc *guc) guc 897 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c GEM_BUG_ON(guc->execbuf_client); guc 899 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c client = guc_client_alloc(guc, GUC_CLIENT_PRIORITY_KMD_NORMAL); guc 904 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c guc->execbuf_client = client; guc 909 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c static void guc_clients_destroy(struct intel_guc *guc) guc 913 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c client = fetch_and_zero(&guc->execbuf_client); guc 944 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c if (intel_guc_is_running(client->guc)) guc 953 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c static int guc_clients_enable(struct intel_guc *guc) guc 955 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c return __guc_client_enable(guc->execbuf_client); guc 958 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c static void guc_clients_disable(struct intel_guc *guc) guc 960 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c if (guc->execbuf_client) guc 961 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c __guc_client_disable(guc->execbuf_client); guc 968 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c int intel_guc_submission_init(struct intel_guc *guc) guc 972 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c if (guc->stage_desc_pool) guc 975 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c ret = guc_stage_desc_pool_create(guc); guc 982 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c GEM_BUG_ON(!guc->stage_desc_pool); guc 984 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c WARN_ON(!guc_verify_doorbells(guc)); guc 985 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c ret = guc_clients_create(guc); guc 992 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c guc_stage_desc_pool_destroy(guc); guc 996 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c void intel_guc_submission_fini(struct intel_guc *guc) guc 998 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c guc_clients_destroy(guc); guc 999 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c WARN_ON(!guc_verify_doorbells(guc)); guc 1001 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c if (guc->stage_desc_pool) guc 1002 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c guc_stage_desc_pool_destroy(guc); guc 1115 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c int intel_guc_submission_enable(struct intel_guc *guc) guc 1117 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c struct intel_gt *gt = guc_to_gt(guc); guc 1139 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c GEM_BUG_ON(!guc->execbuf_client); guc 1141 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c err = guc_clients_enable(guc); guc 1156 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c void intel_guc_submission_disable(struct intel_guc *guc) guc 1158 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c struct intel_gt *gt = guc_to_gt(guc); guc 1163 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c guc_clients_disable(guc); guc 1166 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c static bool __guc_submission_support(struct intel_guc *guc) guc 1171 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c if (!intel_guc_is_supported(guc)) guc 1177 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c void intel_guc_submission_init_early(struct intel_guc *guc) guc 1179 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c guc->submission_supported = __guc_submission_support(guc); guc 42 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h struct intel_guc *guc; guc 59 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h void intel_guc_submission_init_early(struct intel_guc *guc); guc 60 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h int intel_guc_submission_init(struct intel_guc *guc); guc 61 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h int intel_guc_submission_enable(struct intel_guc *guc); guc 62 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h void intel_guc_submission_disable(struct intel_guc *guc); guc 63 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h void intel_guc_submission_fini(struct intel_guc *guc); guc 64 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h int intel_guc_preempt_work_create(struct intel_guc *guc); guc 65 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h void intel_guc_preempt_work_destroy(struct intel_guc *guc); guc 32 drivers/gpu/drm/i915/gt/uc/intel_huc.c struct intel_guc *guc = >->uc.guc; guc 53 drivers/gpu/drm/i915/gt/uc/intel_huc.c vma = intel_guc_allocate_vma(guc, PAGE_SIZE); guc 129 drivers/gpu/drm/i915/gt/uc/intel_huc.c struct intel_guc *guc = >->uc.guc; guc 141 drivers/gpu/drm/i915/gt/uc/intel_huc.c ret = intel_guc_auth_huc(guc, guc 142 drivers/gpu/drm/i915/gt/uc/intel_huc.c intel_guc_ggtt_offset(guc, huc->rsa_data)); guc 88 drivers/gpu/drm/i915/gt/uc/intel_uc.c intel_guc_init_early(&uc->guc); guc 107 drivers/gpu/drm/i915/gt/uc/intel_uc.c intel_guc_init_send_regs(&uc->guc); guc 112 drivers/gpu/drm/i915/gt/uc/intel_uc.c struct intel_guc *guc = &uc->guc; guc 114 drivers/gpu/drm/i915/gt/uc/intel_uc.c if (guc->log.vma && !uc->load_err_log) guc 115 drivers/gpu/drm/i915/gt/uc/intel_uc.c uc->load_err_log = i915_gem_object_get(guc->log.vma->obj); guc 132 drivers/gpu/drm/i915/gt/uc/intel_uc.c static void guc_clear_mmio_msg(struct intel_guc *guc) guc 134 drivers/gpu/drm/i915/gt/uc/intel_uc.c intel_uncore_write(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15), 0); guc 137 drivers/gpu/drm/i915/gt/uc/intel_uc.c static void guc_get_mmio_msg(struct intel_guc *guc) guc 141 drivers/gpu/drm/i915/gt/uc/intel_uc.c spin_lock_irq(&guc->irq_lock); guc 143 drivers/gpu/drm/i915/gt/uc/intel_uc.c val = intel_uncore_read(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15)); guc 144 drivers/gpu/drm/i915/gt/uc/intel_uc.c guc->mmio_msg |= val & guc->msg_enabled_mask; guc 151 drivers/gpu/drm/i915/gt/uc/intel_uc.c guc_clear_mmio_msg(guc); guc 153 drivers/gpu/drm/i915/gt/uc/intel_uc.c spin_unlock_irq(&guc->irq_lock); guc 156 drivers/gpu/drm/i915/gt/uc/intel_uc.c static void guc_handle_mmio_msg(struct intel_guc *guc) guc 158 drivers/gpu/drm/i915/gt/uc/intel_uc.c struct drm_i915_private *i915 = guc_to_gt(guc)->i915; guc 161 drivers/gpu/drm/i915/gt/uc/intel_uc.c GEM_BUG_ON(guc->handler == intel_guc_to_host_event_handler_nop); guc 163 drivers/gpu/drm/i915/gt/uc/intel_uc.c if (!guc->mmio_msg) guc 167 drivers/gpu/drm/i915/gt/uc/intel_uc.c intel_guc_to_host_process_recv_msg(guc, &guc->mmio_msg, 1); guc 170 drivers/gpu/drm/i915/gt/uc/intel_uc.c guc->mmio_msg = 0; guc 173 drivers/gpu/drm/i915/gt/uc/intel_uc.c static void guc_reset_interrupts(struct intel_guc *guc) guc 175 drivers/gpu/drm/i915/gt/uc/intel_uc.c guc->interrupts.reset(guc); guc 178 drivers/gpu/drm/i915/gt/uc/intel_uc.c static void guc_enable_interrupts(struct intel_guc *guc) guc 180 drivers/gpu/drm/i915/gt/uc/intel_uc.c guc->interrupts.enable(guc); guc 183 drivers/gpu/drm/i915/gt/uc/intel_uc.c static void guc_disable_interrupts(struct intel_guc *guc) guc 185 drivers/gpu/drm/i915/gt/uc/intel_uc.c guc->interrupts.disable(guc); guc 188 drivers/gpu/drm/i915/gt/uc/intel_uc.c static inline bool guc_communication_enabled(struct intel_guc *guc) guc 190 drivers/gpu/drm/i915/gt/uc/intel_uc.c return guc->send != intel_guc_send_nop; guc 193 drivers/gpu/drm/i915/gt/uc/intel_uc.c static int guc_enable_communication(struct intel_guc *guc) guc 195 drivers/gpu/drm/i915/gt/uc/intel_uc.c struct drm_i915_private *i915 = guc_to_gt(guc)->i915; guc 198 drivers/gpu/drm/i915/gt/uc/intel_uc.c GEM_BUG_ON(guc_communication_enabled(guc)); guc 204 drivers/gpu/drm/i915/gt/uc/intel_uc.c ret = intel_guc_ct_enable(&guc->ct); guc 208 drivers/gpu/drm/i915/gt/uc/intel_uc.c guc->send = intel_guc_send_ct; guc 209 drivers/gpu/drm/i915/gt/uc/intel_uc.c guc->handler = intel_guc_to_host_event_handler_ct; guc 212 drivers/gpu/drm/i915/gt/uc/intel_uc.c guc_get_mmio_msg(guc); guc 213 drivers/gpu/drm/i915/gt/uc/intel_uc.c guc_handle_mmio_msg(guc); guc 215 drivers/gpu/drm/i915/gt/uc/intel_uc.c guc_enable_interrupts(guc); guc 219 drivers/gpu/drm/i915/gt/uc/intel_uc.c intel_guc_to_host_event_handler_ct(guc); guc 227 drivers/gpu/drm/i915/gt/uc/intel_uc.c static void guc_stop_communication(struct intel_guc *guc) guc 229 drivers/gpu/drm/i915/gt/uc/intel_uc.c intel_guc_ct_stop(&guc->ct); guc 231 drivers/gpu/drm/i915/gt/uc/intel_uc.c guc->send = intel_guc_send_nop; guc 232 drivers/gpu/drm/i915/gt/uc/intel_uc.c guc->handler = intel_guc_to_host_event_handler_nop; guc 234 drivers/gpu/drm/i915/gt/uc/intel_uc.c guc_clear_mmio_msg(guc); guc 237 drivers/gpu/drm/i915/gt/uc/intel_uc.c static void guc_disable_communication(struct intel_guc *guc) guc 244 drivers/gpu/drm/i915/gt/uc/intel_uc.c guc_clear_mmio_msg(guc); guc 246 drivers/gpu/drm/i915/gt/uc/intel_uc.c guc_disable_interrupts(guc); guc 248 drivers/gpu/drm/i915/gt/uc/intel_uc.c guc->send = intel_guc_send_nop; guc 249 drivers/gpu/drm/i915/gt/uc/intel_uc.c guc->handler = intel_guc_to_host_event_handler_nop; guc 251 drivers/gpu/drm/i915/gt/uc/intel_uc.c intel_guc_ct_disable(&guc->ct); guc 259 drivers/gpu/drm/i915/gt/uc/intel_uc.c guc_get_mmio_msg(guc); guc 272 drivers/gpu/drm/i915/gt/uc/intel_uc.c err = intel_uc_fw_fetch(&uc->guc.fw, i915); guc 288 drivers/gpu/drm/i915/gt/uc/intel_uc.c intel_uc_fw_cleanup_fetch(&uc->guc.fw); guc 293 drivers/gpu/drm/i915/gt/uc/intel_uc.c struct intel_guc *guc = &uc->guc; guc 303 drivers/gpu/drm/i915/gt/uc/intel_uc.c ret = intel_guc_init(guc); guc 315 drivers/gpu/drm/i915/gt/uc/intel_uc.c struct intel_guc *guc = &uc->guc; guc 323 drivers/gpu/drm/i915/gt/uc/intel_uc.c intel_guc_fini(guc); guc 330 drivers/gpu/drm/i915/gt/uc/intel_uc.c struct intel_guc *guc = &uc->guc; guc 336 drivers/gpu/drm/i915/gt/uc/intel_uc.c intel_guc_sanitize(guc); guc 415 drivers/gpu/drm/i915/gt/uc/intel_uc.c struct intel_guc *guc = &uc->guc; guc 430 drivers/gpu/drm/i915/gt/uc/intel_uc.c if (!intel_uc_fw_is_available(&guc->fw)) { guc 432 drivers/gpu/drm/i915/gt/uc/intel_uc.c intel_uc_fw_is_overridden(&guc->fw) || guc 434 drivers/gpu/drm/i915/gt/uc/intel_uc.c intel_uc_fw_status_to_error(guc->fw.status) : 0; guc 442 drivers/gpu/drm/i915/gt/uc/intel_uc.c guc_reset_interrupts(guc); guc 461 drivers/gpu/drm/i915/gt/uc/intel_uc.c intel_guc_ads_reset(guc); guc 462 drivers/gpu/drm/i915/gt/uc/intel_uc.c intel_guc_write_params(guc); guc 463 drivers/gpu/drm/i915/gt/uc/intel_uc.c ret = intel_guc_fw_upload(guc); guc 475 drivers/gpu/drm/i915/gt/uc/intel_uc.c ret = guc_enable_communication(guc); guc 481 drivers/gpu/drm/i915/gt/uc/intel_uc.c ret = intel_guc_sample_forcewake(guc); guc 486 drivers/gpu/drm/i915/gt/uc/intel_uc.c ret = intel_guc_submission_enable(guc); guc 492 drivers/gpu/drm/i915/gt/uc/intel_uc.c intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_GUC), guc->fw.path, guc 493 drivers/gpu/drm/i915/gt/uc/intel_uc.c guc->fw.major_ver_found, guc->fw.minor_ver_found, guc 512 drivers/gpu/drm/i915/gt/uc/intel_uc.c guc_disable_communication(guc); guc 532 drivers/gpu/drm/i915/gt/uc/intel_uc.c struct intel_guc *guc = &uc->guc; guc 534 drivers/gpu/drm/i915/gt/uc/intel_uc.c if (!intel_guc_is_running(guc)) guc 538 drivers/gpu/drm/i915/gt/uc/intel_uc.c intel_guc_submission_disable(guc); guc 540 drivers/gpu/drm/i915/gt/uc/intel_uc.c guc_disable_communication(guc); guc 552 drivers/gpu/drm/i915/gt/uc/intel_uc.c struct intel_guc *guc = &uc->guc; guc 554 drivers/gpu/drm/i915/gt/uc/intel_uc.c if (!intel_guc_is_running(guc)) guc 557 drivers/gpu/drm/i915/gt/uc/intel_uc.c guc_stop_communication(guc); guc 563 drivers/gpu/drm/i915/gt/uc/intel_uc.c struct intel_guc *guc = &uc->guc; guc 566 drivers/gpu/drm/i915/gt/uc/intel_uc.c if (!intel_guc_is_running(guc)) guc 569 drivers/gpu/drm/i915/gt/uc/intel_uc.c err = intel_guc_suspend(guc); guc 573 drivers/gpu/drm/i915/gt/uc/intel_uc.c guc_disable_communication(guc); guc 578 drivers/gpu/drm/i915/gt/uc/intel_uc.c struct intel_guc *guc = &uc->guc; guc 581 drivers/gpu/drm/i915/gt/uc/intel_uc.c if (!intel_guc_is_running(guc)) guc 590 drivers/gpu/drm/i915/gt/uc/intel_uc.c struct intel_guc *guc = &uc->guc; guc 593 drivers/gpu/drm/i915/gt/uc/intel_uc.c if (!intel_guc_is_running(guc)) guc 597 drivers/gpu/drm/i915/gt/uc/intel_uc.c GEM_BUG_ON(enable_communication == guc_communication_enabled(guc)); guc 600 drivers/gpu/drm/i915/gt/uc/intel_uc.c guc_enable_communication(guc); guc 602 drivers/gpu/drm/i915/gt/uc/intel_uc.c err = intel_guc_resume(guc); guc 14 drivers/gpu/drm/i915/gt/uc/intel_uc.h struct intel_guc guc; guc 39 drivers/gpu/drm/i915/gt/uc/intel_uc.h return intel_guc_is_supported(&uc->guc); guc 44 drivers/gpu/drm/i915/gt/uc/intel_uc.h return intel_guc_is_enabled(&uc->guc); guc 49 drivers/gpu/drm/i915/gt/uc/intel_uc.h return intel_guc_is_submission_supported(&uc->guc); guc 54 drivers/gpu/drm/i915/gt/uc/intel_uc.h return intel_guc_is_submission_supported(&uc->guc); guc 19 drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c return container_of(uc_fw, struct intel_gt, uc.guc.fw); guc 14 drivers/gpu/drm/i915/gt/uc/selftest_guc.c static bool available_dbs(struct intel_guc *guc, u32 priority) guc 28 drivers/gpu/drm/i915/gt/uc/selftest_guc.c id = find_next_zero_bit(guc->doorbell_bitmap, end, offset); guc 35 drivers/gpu/drm/i915/gt/uc/selftest_guc.c static int check_all_doorbells(struct intel_guc *guc) guc 41 drivers/gpu/drm/i915/gt/uc/selftest_guc.c if (!doorbell_ok(guc, db_id)) { guc 98 drivers/gpu/drm/i915/gt/uc/selftest_guc.c return !client || doorbell_ok(client->guc, client->doorbell_id); guc 115 drivers/gpu/drm/i915/gt/uc/selftest_guc.c struct intel_guc *guc; guc 122 drivers/gpu/drm/i915/gt/uc/selftest_guc.c guc = &dev_priv->gt.uc.guc; guc 123 drivers/gpu/drm/i915/gt/uc/selftest_guc.c if (!guc) { guc 129 drivers/gpu/drm/i915/gt/uc/selftest_guc.c err = check_all_doorbells(guc); guc 137 drivers/gpu/drm/i915/gt/uc/selftest_guc.c guc_clients_disable(guc); guc 138 drivers/gpu/drm/i915/gt/uc/selftest_guc.c guc_clients_destroy(guc); guc 139 drivers/gpu/drm/i915/gt/uc/selftest_guc.c if (guc->execbuf_client) { guc 145 drivers/gpu/drm/i915/gt/uc/selftest_guc.c err = guc_clients_create(guc); guc 150 drivers/gpu/drm/i915/gt/uc/selftest_guc.c GEM_BUG_ON(!guc->execbuf_client); guc 152 drivers/gpu/drm/i915/gt/uc/selftest_guc.c err = validate_client(guc->execbuf_client, guc 160 drivers/gpu/drm/i915/gt/uc/selftest_guc.c if (!has_doorbell(guc->execbuf_client)) { guc 167 drivers/gpu/drm/i915/gt/uc/selftest_guc.c guc_clients_enable(guc); guc 170 drivers/gpu/drm/i915/gt/uc/selftest_guc.c if (!client_doorbell_in_sync(guc->execbuf_client)) { guc 180 drivers/gpu/drm/i915/gt/uc/selftest_guc.c err = create_doorbell(guc->execbuf_client); guc 187 drivers/gpu/drm/i915/gt/uc/selftest_guc.c guc_clients_disable(guc); guc 188 drivers/gpu/drm/i915/gt/uc/selftest_guc.c guc_clients_destroy(guc); guc 189 drivers/gpu/drm/i915/gt/uc/selftest_guc.c guc_clients_create(guc); guc 190 drivers/gpu/drm/i915/gt/uc/selftest_guc.c guc_clients_enable(guc); guc 206 drivers/gpu/drm/i915/gt/uc/selftest_guc.c struct intel_guc *guc; guc 214 drivers/gpu/drm/i915/gt/uc/selftest_guc.c guc = &dev_priv->gt.uc.guc; guc 215 drivers/gpu/drm/i915/gt/uc/selftest_guc.c if (!guc) { guc 221 drivers/gpu/drm/i915/gt/uc/selftest_guc.c err = check_all_doorbells(guc); guc 226 drivers/gpu/drm/i915/gt/uc/selftest_guc.c clients[i] = guc_client_alloc(guc, i % GUC_CLIENT_PRIORITY_NUM); guc 241 drivers/gpu/drm/i915/gt/uc/selftest_guc.c if (available_dbs(guc, i % GUC_CLIENT_PRIORITY_NUM)) { guc 285 drivers/gpu/drm/i915/gt/uc/selftest_guc.c err = check_all_doorbells(guc); guc 1817 drivers/gpu/drm/i915/i915_debugfs.c intel_uc_fw_dump(&dev_priv->gt.uc.guc.fw, &p); guc 1860 drivers/gpu/drm/i915/i915_debugfs.c struct intel_guc_log *log = &dev_priv->gt.uc.guc.log; guc 1884 drivers/gpu/drm/i915/i915_debugfs.c const struct intel_guc *guc = &dev_priv->gt.uc.guc; guc 1885 drivers/gpu/drm/i915/i915_debugfs.c struct intel_guc_client *client = guc->execbuf_client; guc 1895 drivers/gpu/drm/i915/i915_debugfs.c GEM_BUG_ON(!guc->execbuf_client); guc 1898 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap); guc 1899 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, "Doorbell next cacheline: 0x%x\n", guc->db_cacheline); guc 1916 drivers/gpu/drm/i915/i915_debugfs.c const struct intel_guc *guc = &dev_priv->gt.uc.guc; guc 1917 drivers/gpu/drm/i915/i915_debugfs.c struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr; guc 1979 drivers/gpu/drm/i915/i915_debugfs.c else if (dev_priv->gt.uc.guc.log.vma) guc 1980 drivers/gpu/drm/i915/i915_debugfs.c obj = dev_priv->gt.uc.guc.log.vma->obj; guc 2011 drivers/gpu/drm/i915/i915_debugfs.c *val = intel_guc_log_get_level(&dev_priv->gt.uc.guc.log); guc 2023 drivers/gpu/drm/i915/i915_debugfs.c return intel_guc_log_set_level(&dev_priv->gt.uc.guc.log, val); guc 2033 drivers/gpu/drm/i915/i915_debugfs.c struct intel_guc *guc = &i915->gt.uc.guc; guc 2034 drivers/gpu/drm/i915/i915_debugfs.c struct intel_guc_log *log = &guc->log; guc 2036 drivers/gpu/drm/i915/i915_debugfs.c if (!intel_guc_is_running(guc)) guc 2059 drivers/gpu/drm/i915/i915_debugfs.c struct intel_guc *guc = &i915->gt.uc.guc; guc 2061 drivers/gpu/drm/i915/i915_debugfs.c intel_guc_log_relay_close(&guc->log); guc 1478 drivers/gpu/drm/i915/i915_gpu_error.c memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw)); guc 1485 drivers/gpu/drm/i915/i915_gpu_error.c error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, ALLOW_FAIL); guc 1488 drivers/gpu/drm/i915/i915_gpu_error.c uc->guc.log.vma, guc 418 drivers/gpu/drm/i915/i915_irq.c void gen9_reset_guc_interrupts(struct intel_guc *guc) guc 420 drivers/gpu/drm/i915/i915_irq.c struct intel_gt *gt = guc_to_gt(guc); guc 429 drivers/gpu/drm/i915/i915_irq.c void gen9_enable_guc_interrupts(struct intel_guc *guc) guc 431 drivers/gpu/drm/i915/i915_irq.c struct intel_gt *gt = guc_to_gt(guc); guc 436 drivers/gpu/drm/i915/i915_irq.c if (!guc->interrupts.enabled) { guc 440 drivers/gpu/drm/i915/i915_irq.c guc->interrupts.enabled = true; guc 446 drivers/gpu/drm/i915/i915_irq.c void gen9_disable_guc_interrupts(struct intel_guc *guc) guc 448 drivers/gpu/drm/i915/i915_irq.c struct intel_gt *gt = guc_to_gt(guc); guc 453 drivers/gpu/drm/i915/i915_irq.c guc->interrupts.enabled = false; guc 460 drivers/gpu/drm/i915/i915_irq.c gen9_reset_guc_interrupts(guc); guc 463 drivers/gpu/drm/i915/i915_irq.c void gen11_reset_guc_interrupts(struct intel_guc *guc) guc 465 drivers/gpu/drm/i915/i915_irq.c struct intel_gt *gt = guc_to_gt(guc); guc 472 drivers/gpu/drm/i915/i915_irq.c void gen11_enable_guc_interrupts(struct intel_guc *guc) guc 474 drivers/gpu/drm/i915/i915_irq.c struct intel_gt *gt = guc_to_gt(guc); guc 477 drivers/gpu/drm/i915/i915_irq.c if (!guc->interrupts.enabled) { guc 483 drivers/gpu/drm/i915/i915_irq.c guc->interrupts.enabled = true; guc 488 drivers/gpu/drm/i915/i915_irq.c void gen11_disable_guc_interrupts(struct intel_guc *guc) guc 490 drivers/gpu/drm/i915/i915_irq.c struct intel_gt *gt = guc_to_gt(guc); guc 493 drivers/gpu/drm/i915/i915_irq.c guc->interrupts.enabled = false; guc 501 drivers/gpu/drm/i915/i915_irq.c gen11_reset_guc_interrupts(guc); guc 109 drivers/gpu/drm/i915/i915_irq.h void gen9_reset_guc_interrupts(struct intel_guc *guc); guc 110 drivers/gpu/drm/i915/i915_irq.h void gen9_enable_guc_interrupts(struct intel_guc *guc); guc 111 drivers/gpu/drm/i915/i915_irq.h void gen9_disable_guc_interrupts(struct intel_guc *guc); guc 112 drivers/gpu/drm/i915/i915_irq.h void gen11_reset_guc_interrupts(struct intel_guc *guc); guc 113 drivers/gpu/drm/i915/i915_irq.h void gen11_enable_guc_interrupts(struct intel_guc *guc); guc 114 drivers/gpu/drm/i915/i915_irq.h void gen11_disable_guc_interrupts(struct intel_guc *guc); guc 225 drivers/gpu/drm/i915/intel_wopcm.c u32 guc_fw_size = intel_uc_fw_get_upload_size(>->uc.guc.fw); guc 235 drivers/gpu/drm/i915/intel_wopcm.c GEM_BUG_ON(wopcm->guc.base); guc 236 drivers/gpu/drm/i915/intel_wopcm.c GEM_BUG_ON(wopcm->guc.size); guc 275 drivers/gpu/drm/i915/intel_wopcm.c wopcm->guc.base = guc_wopcm_base; guc 276 drivers/gpu/drm/i915/intel_wopcm.c wopcm->guc.size = guc_wopcm_size; guc 277 drivers/gpu/drm/i915/intel_wopcm.c GEM_BUG_ON(!wopcm->guc.base); guc 278 drivers/gpu/drm/i915/intel_wopcm.c GEM_BUG_ON(!wopcm->guc.size); guc 24 drivers/gpu/drm/i915/intel_wopcm.h } guc; guc 39 drivers/gpu/drm/i915/intel_wopcm.h return wopcm->guc.base; guc 54 drivers/gpu/drm/i915/intel_wopcm.h return wopcm->guc.size; guc 35 drivers/gpu/drm/i915/selftests/i915_live_selftests.h selftest(guc, intel_guc_live_selftest)