HUBP0_DCHUBP_CNTL  244 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_BLANK_EN, mask_sh),\
HUBP0_DCHUBP_CNTL  245 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\
HUBP0_DCHUBP_CNTL  246 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\
HUBP0_DCHUBP_CNTL  247 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, mask_sh),\
HUBP0_DCHUBP_CNTL  248 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\
HUBP0_DCHUBP_CNTL  249 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\
HUBP0_DCHUBP_CNTL  250 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE, mask_sh),\
HUBP0_DCHUBP_CNTL  111 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\
HUBP0_DCHUBP_CNTL  112 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h 	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\
HUBP0_DCHUBP_CNTL   86 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h 	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\
HUBP0_DCHUBP_CNTL   87 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.h 	HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\