grpen0            154 arch/arm64/kvm/vgic-sys-reg-v3.c 		vmcr.grpen0 = (p->regval & ICC_IGRPEN0_EL1_MASK) >>
grpen0            158 arch/arm64/kvm/vgic-sys-reg-v3.c 		p->regval = (vmcr.grpen0 << ICC_IGRPEN0_EL1_SHIFT) &
grpen0            274 virt/kvm/arm/vgic/vgic-mmio-v2.c 		val = vmcr.grpen0 << GIC_CPU_CTRL_EnableGrp0_SHIFT;
grpen0            321 virt/kvm/arm/vgic/vgic-mmio-v2.c 		vmcr.grpen0 = !!(val & GIC_CPU_CTRL_EnableGrp0);
grpen0            225 virt/kvm/arm/vgic/vgic-v2.c 	vmcr = (vmcrp->grpen0 << GICH_VMCR_ENABLE_GRP0_SHIFT) &
grpen0            254 virt/kvm/arm/vgic/vgic-v2.c 	vmcrp->grpen0 = (vmcr & GICH_VMCR_ENABLE_GRP0_MASK) >>
grpen0            229 virt/kvm/arm/vgic/vgic-v3.c 	vmcr |= (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK;
grpen0            262 virt/kvm/arm/vgic/vgic-v3.c 	vmcrp->grpen0 = (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT;
grpen0            136 virt/kvm/arm/vgic/vgic.h 	u32	grpen0;