graphic_level 893 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c SMU71_Discrete_GraphicsLevel *graphic_level) graphic_level 898 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c result = iceland_calculate_sclk_params(hwmgr, engine_clock, graphic_level); graphic_level 903 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c &graphic_level->MinVddc); graphic_level 908 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c graphic_level->SclkFrequency = engine_clock; graphic_level 909 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c graphic_level->MinVddcPhases = 1; graphic_level 915 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c &graphic_level->MinVddcPhases); graphic_level 918 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c graphic_level->ActivityLevel = data->current_profile_setting.sclk_activity; graphic_level 920 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c graphic_level->CcPwrDynRm = 0; graphic_level 921 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c graphic_level->CcPwrDynRm1 = 0; graphic_level 923 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c graphic_level->EnabledForActivity = 0; graphic_level 925 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c graphic_level->EnabledForThrottle = 1; graphic_level 926 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c graphic_level->UpHyst = data->current_profile_setting.sclk_up_hyst; graphic_level 927 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c graphic_level->DownHyst = data->current_profile_setting.sclk_down_hyst; graphic_level 928 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c graphic_level->VoltageDownHyst = 0; graphic_level 929 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c graphic_level->PowerThrottle = 0; graphic_level 936 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c graphic_level->DeepSleepDivId = graphic_level 941 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; graphic_level 944 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c graphic_level->MinVddc = PP_HOST_TO_SMC_UL(graphic_level->MinVddc * VOLTAGE_SCALE); graphic_level 945 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases); graphic_level 946 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency); graphic_level 947 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel); graphic_level 948 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3); graphic_level 949 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4); graphic_level 950 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum); graphic_level 951 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2); graphic_level 952 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm); graphic_level 953 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1); graphic_level 618 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c SMU72_Discrete_GraphicsLevel *graphic_level) graphic_level 627 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level); graphic_level 637 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c &graphic_level->MinVoltage, &mvdd); graphic_level 643 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c graphic_level->SclkFrequency = engine_clock; graphic_level 645 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c graphic_level->ActivityLevel = data->current_profile_setting.sclk_activity; graphic_level 647 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c graphic_level->CcPwrDynRm = 0; graphic_level 648 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c graphic_level->CcPwrDynRm1 = 0; graphic_level 650 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c graphic_level->EnabledForActivity = 0; graphic_level 652 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c graphic_level->EnabledForThrottle = 1; graphic_level 653 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c graphic_level->UpHyst = data->current_profile_setting.sclk_up_hyst; graphic_level 654 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c graphic_level->DownHyst = data->current_profile_setting.sclk_down_hyst; graphic_level 655 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c graphic_level->VoltageDownHyst = 0; graphic_level 656 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c graphic_level->PowerThrottle = 0; graphic_level 663 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c graphic_level->DeepSleepDivId = graphic_level 668 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; graphic_level 673 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency); graphic_level 674 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel); graphic_level 675 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3); graphic_level 676 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4); graphic_level 677 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum); graphic_level 678 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2); graphic_level 679 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm); graphic_level 680 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1); graphic_level 3218 drivers/gpu/drm/radeon/ci_dpm.c SMU7_Discrete_GraphicsLevel *graphic_level) graphic_level 3223 drivers/gpu/drm/radeon/ci_dpm.c ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level); graphic_level 3229 drivers/gpu/drm/radeon/ci_dpm.c engine_clock, &graphic_level->MinVddc); graphic_level 3233 drivers/gpu/drm/radeon/ci_dpm.c graphic_level->SclkFrequency = engine_clock; graphic_level 3235 drivers/gpu/drm/radeon/ci_dpm.c graphic_level->Flags = 0; graphic_level 3236 drivers/gpu/drm/radeon/ci_dpm.c graphic_level->MinVddcPhases = 1; graphic_level 3242 drivers/gpu/drm/radeon/ci_dpm.c &graphic_level->MinVddcPhases); graphic_level 3244 drivers/gpu/drm/radeon/ci_dpm.c graphic_level->ActivityLevel = sclk_activity_level_t; graphic_level 3246 drivers/gpu/drm/radeon/ci_dpm.c graphic_level->CcPwrDynRm = 0; graphic_level 3247 drivers/gpu/drm/radeon/ci_dpm.c graphic_level->CcPwrDynRm1 = 0; graphic_level 3248 drivers/gpu/drm/radeon/ci_dpm.c graphic_level->EnabledForThrottle = 1; graphic_level 3249 drivers/gpu/drm/radeon/ci_dpm.c graphic_level->UpH = 0; graphic_level 3250 drivers/gpu/drm/radeon/ci_dpm.c graphic_level->DownH = 0; graphic_level 3251 drivers/gpu/drm/radeon/ci_dpm.c graphic_level->VoltageDownH = 0; graphic_level 3252 drivers/gpu/drm/radeon/ci_dpm.c graphic_level->PowerThrottle = 0; graphic_level 3255 drivers/gpu/drm/radeon/ci_dpm.c graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev, graphic_level 3259 drivers/gpu/drm/radeon/ci_dpm.c graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; graphic_level 3261 drivers/gpu/drm/radeon/ci_dpm.c graphic_level->Flags = cpu_to_be32(graphic_level->Flags); graphic_level 3262 drivers/gpu/drm/radeon/ci_dpm.c graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE); graphic_level 3263 drivers/gpu/drm/radeon/ci_dpm.c graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases); graphic_level 3264 drivers/gpu/drm/radeon/ci_dpm.c graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency); graphic_level 3265 drivers/gpu/drm/radeon/ci_dpm.c graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel); graphic_level 3266 drivers/gpu/drm/radeon/ci_dpm.c graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3); graphic_level 3267 drivers/gpu/drm/radeon/ci_dpm.c graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4); graphic_level 3268 drivers/gpu/drm/radeon/ci_dpm.c graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum); graphic_level 3269 drivers/gpu/drm/radeon/ci_dpm.c graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2); graphic_level 3270 drivers/gpu/drm/radeon/ci_dpm.c graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm); graphic_level 3271 drivers/gpu/drm/radeon/ci_dpm.c graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);