gr 467 arch/ia64/include/asm/pal.h gr : 1, /* General registers gr 684 arch/ia64/include/asm/pal.h #define pmci_proc_gpr_valid pme_processor.gr gr 883 arch/ia64/include/asm/sal.h u64 gr[4]; gr 216 arch/ia64/include/uapi/asm/ptrace.h unsigned long gr[32]; gr 885 arch/ia64/kernel/ptrace.c retval |= __copy_to_user(&ppr->gr[1], &pt->r1, sizeof(long)); gr 886 arch/ia64/kernel/ptrace.c retval |= __copy_to_user(&ppr->gr[2], &pt->r2, sizeof(long) *2); gr 893 arch/ia64/kernel/ptrace.c retval |= __put_user(val, &ppr->gr[i]); gr 898 arch/ia64/kernel/ptrace.c retval |= __copy_to_user(&ppr->gr[8], &pt->r8, sizeof(long) * 4); gr 902 arch/ia64/kernel/ptrace.c retval |= __copy_to_user(&ppr->gr[12], &pt->r12, sizeof(long) * 2); gr 903 arch/ia64/kernel/ptrace.c retval |= __copy_to_user(&ppr->gr[14], &pt->r14, sizeof(long)); gr 904 arch/ia64/kernel/ptrace.c retval |= __copy_to_user(&ppr->gr[15], &pt->r15, sizeof(long)); gr 908 arch/ia64/kernel/ptrace.c retval |= __copy_to_user(&ppr->gr[16], &pt->r16, sizeof(long) * 16); gr 1021 arch/ia64/kernel/ptrace.c retval |= __copy_from_user(&pt->r1, &ppr->gr[1], sizeof(long)); gr 1022 arch/ia64/kernel/ptrace.c retval |= __copy_from_user(&pt->r2, &ppr->gr[2], sizeof(long) * 2); gr 1027 arch/ia64/kernel/ptrace.c retval |= __get_user(val, &ppr->gr[i]); gr 1035 arch/ia64/kernel/ptrace.c retval |= __copy_from_user(&pt->r8, &ppr->gr[8], sizeof(long) * 4); gr 1039 arch/ia64/kernel/ptrace.c retval |= __copy_from_user(&pt->r12, &ppr->gr[12], sizeof(long) * 2); gr 1040 arch/ia64/kernel/ptrace.c retval |= __copy_from_user(&pt->r14, &ppr->gr[14], sizeof(long)); gr 1041 arch/ia64/kernel/ptrace.c retval |= __copy_from_user(&pt->r15, &ppr->gr[15], sizeof(long)); gr 1045 arch/ia64/kernel/ptrace.c retval |= __copy_from_user(&pt->r16, &ppr->gr[16], sizeof(long) * 16); gr 866 arch/ia64/kernel/unwind.c desc_br_gr (unsigned char brmask, unsigned char gr, struct unw_state_record *sr) gr 873 arch/ia64/kernel/unwind.c sr->region_start + sr->region_len - 1, gr++); gr 933 arch/ia64/kernel/unwind.c desc_gr_gr (unsigned char grmask, unsigned char gr, struct unw_state_record *sr) gr 940 arch/ia64/kernel/unwind.c sr->region_start + sr->region_len - 1, gr++); gr 1155 arch/ia64/kernel/unwind.c #define UNW_DEC_PROLOGUE_GR(fmt,r,m,gr,arg) desc_prologue(0,r,m,gr,arg) gr 98 arch/parisc/include/asm/assembly.h .macro tophys_r1 gr gr 103 arch/parisc/include/asm/assembly.h .macro tovirt_r1 gr gr 196 arch/parisc/include/asm/compat.h return (void __user *)regs->gr[30]; gr 280 arch/parisc/include/asm/elf.h for (i = 0; i < 32; i++) dst[i] = pt->gr[i]; \ gr 334 arch/parisc/include/asm/elf.h #define ELF_PLAT_INIT(_r, load_addr) _r->gr[23] = 0 gr 146 arch/parisc/include/asm/processor.h .regs = { .gr = { 0, }, \ gr 266 arch/parisc/include/asm/processor.h regs->gr[ 0] = USER_PSW | (USER_WIDE_MODE ? PSW_W : 0); \ gr 271 arch/parisc/include/asm/processor.h regs->gr[30] = (((unsigned long)sp + 63) &~ 63) | (USER_WIDE_MODE ? 1 : 0); \ gr 272 arch/parisc/include/asm/processor.h regs->gr[31] = pc; \ gr 274 arch/parisc/include/asm/processor.h get_user(regs->gr[25], (argv - 1)); \ gr 275 arch/parisc/include/asm/processor.h regs->gr[24] = (long) argv; \ gr 276 arch/parisc/include/asm/processor.h regs->gr[23] = 0; \ gr 288 arch/parisc/include/asm/processor.h #define KSTK_ESP(tsk) ((tsk)->thread.regs.gr[30]) gr 20 arch/parisc/include/asm/ptrace.h #define user_stack_pointer(regs) ((regs)->gr[30]) gr 25 arch/parisc/include/asm/ptrace.h return regs->gr[28]; gr 40 arch/parisc/include/asm/ptrace.h #define kernel_stack_pointer(regs) ((regs)->gr[30]) gr 38 arch/parisc/include/asm/special_insns.h #define mtctl(gr, cr) \ gr 41 arch/parisc/include/asm/special_insns.h : "r" (gr), "i" (cr) : "memory") gr 17 arch/parisc/include/asm/syscall.h return regs->gr[20]; gr 24 arch/parisc/include/asm/syscall.h args[5] = regs->gr[21]; gr 25 arch/parisc/include/asm/syscall.h args[4] = regs->gr[22]; gr 26 arch/parisc/include/asm/syscall.h args[3] = regs->gr[23]; gr 27 arch/parisc/include/asm/syscall.h args[2] = regs->gr[24]; gr 28 arch/parisc/include/asm/syscall.h args[1] = regs->gr[25]; gr 29 arch/parisc/include/asm/syscall.h args[0] = regs->gr[26]; gr 35 arch/parisc/include/asm/syscall.h unsigned long error = regs->gr[28]; gr 42 arch/parisc/include/asm/syscall.h return regs->gr[28]; gr 49 arch/parisc/include/asm/syscall.h regs->gr[28] = error ? error : val; gr 641 arch/parisc/include/uapi/asm/pdc.h unsigned int gr[32]; gr 674 arch/parisc/include/uapi/asm/pdc.h unsigned long long gr[32]; gr 25 arch/parisc/include/uapi/asm/ptrace.h unsigned long gr[32]; /* PSW is in gr[0] */ gr 52 arch/parisc/include/uapi/asm/ptrace.h unsigned long gr[32]; /* PSW is in gr[0] */ gr 54 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_PSW, offsetof(struct task_struct, thread.regs.gr[ 0])); gr 55 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR1, offsetof(struct task_struct, thread.regs.gr[ 1])); gr 56 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR2, offsetof(struct task_struct, thread.regs.gr[ 2])); gr 57 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR3, offsetof(struct task_struct, thread.regs.gr[ 3])); gr 58 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR4, offsetof(struct task_struct, thread.regs.gr[ 4])); gr 59 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR5, offsetof(struct task_struct, thread.regs.gr[ 5])); gr 60 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR6, offsetof(struct task_struct, thread.regs.gr[ 6])); gr 61 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR7, offsetof(struct task_struct, thread.regs.gr[ 7])); gr 62 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR8, offsetof(struct task_struct, thread.regs.gr[ 8])); gr 63 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR9, offsetof(struct task_struct, thread.regs.gr[ 9])); gr 64 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR10, offsetof(struct task_struct, thread.regs.gr[10])); gr 65 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR11, offsetof(struct task_struct, thread.regs.gr[11])); gr 66 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR12, offsetof(struct task_struct, thread.regs.gr[12])); gr 67 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR13, offsetof(struct task_struct, thread.regs.gr[13])); gr 68 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR14, offsetof(struct task_struct, thread.regs.gr[14])); gr 69 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR15, offsetof(struct task_struct, thread.regs.gr[15])); gr 70 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR16, offsetof(struct task_struct, thread.regs.gr[16])); gr 71 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR17, offsetof(struct task_struct, thread.regs.gr[17])); gr 72 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR18, offsetof(struct task_struct, thread.regs.gr[18])); gr 73 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR19, offsetof(struct task_struct, thread.regs.gr[19])); gr 74 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR20, offsetof(struct task_struct, thread.regs.gr[20])); gr 75 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR21, offsetof(struct task_struct, thread.regs.gr[21])); gr 76 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR22, offsetof(struct task_struct, thread.regs.gr[22])); gr 77 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR23, offsetof(struct task_struct, thread.regs.gr[23])); gr 78 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR24, offsetof(struct task_struct, thread.regs.gr[24])); gr 79 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR25, offsetof(struct task_struct, thread.regs.gr[25])); gr 80 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR26, offsetof(struct task_struct, thread.regs.gr[26])); gr 81 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR27, offsetof(struct task_struct, thread.regs.gr[27])); gr 82 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR28, offsetof(struct task_struct, thread.regs.gr[28])); gr 83 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR29, offsetof(struct task_struct, thread.regs.gr[29])); gr 84 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR30, offsetof(struct task_struct, thread.regs.gr[30])); gr 85 arch/parisc/kernel/asm-offsets.c DEFINE(TASK_PT_GR31, offsetof(struct task_struct, thread.regs.gr[31])); gr 143 arch/parisc/kernel/asm-offsets.c DEFINE(PT_PSW, offsetof(struct pt_regs, gr[ 0])); gr 144 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR1, offsetof(struct pt_regs, gr[ 1])); gr 145 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR2, offsetof(struct pt_regs, gr[ 2])); gr 146 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR3, offsetof(struct pt_regs, gr[ 3])); gr 147 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR4, offsetof(struct pt_regs, gr[ 4])); gr 148 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR5, offsetof(struct pt_regs, gr[ 5])); gr 149 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR6, offsetof(struct pt_regs, gr[ 6])); gr 150 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR7, offsetof(struct pt_regs, gr[ 7])); gr 151 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR8, offsetof(struct pt_regs, gr[ 8])); gr 152 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR9, offsetof(struct pt_regs, gr[ 9])); gr 153 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR10, offsetof(struct pt_regs, gr[10])); gr 154 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR11, offsetof(struct pt_regs, gr[11])); gr 155 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR12, offsetof(struct pt_regs, gr[12])); gr 156 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR13, offsetof(struct pt_regs, gr[13])); gr 157 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR14, offsetof(struct pt_regs, gr[14])); gr 158 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR15, offsetof(struct pt_regs, gr[15])); gr 159 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR16, offsetof(struct pt_regs, gr[16])); gr 160 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR17, offsetof(struct pt_regs, gr[17])); gr 161 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR18, offsetof(struct pt_regs, gr[18])); gr 162 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR19, offsetof(struct pt_regs, gr[19])); gr 163 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR20, offsetof(struct pt_regs, gr[20])); gr 164 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR21, offsetof(struct pt_regs, gr[21])); gr 165 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR22, offsetof(struct pt_regs, gr[22])); gr 166 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR23, offsetof(struct pt_regs, gr[23])); gr 167 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR24, offsetof(struct pt_regs, gr[24])); gr 168 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR25, offsetof(struct pt_regs, gr[25])); gr 169 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR26, offsetof(struct pt_regs, gr[26])); gr 170 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR27, offsetof(struct pt_regs, gr[27])); gr 171 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR28, offsetof(struct pt_regs, gr[28])); gr 172 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR29, offsetof(struct pt_regs, gr[29])); gr 173 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR30, offsetof(struct pt_regs, gr[30])); gr 174 arch/parisc/kernel/asm-offsets.c DEFINE(PT_GR31, offsetof(struct pt_regs, gr[31])); gr 402 arch/parisc/kernel/irq.c unsigned long sp = regs->gr[30]; gr 64 arch/parisc/kernel/kgdb.c struct parisc_gdb_regs *gr = (struct parisc_gdb_regs *)gdb_regs; gr 66 arch/parisc/kernel/kgdb.c memset(gr, 0, sizeof(struct parisc_gdb_regs)); gr 68 arch/parisc/kernel/kgdb.c memcpy(gr->gpr, regs->gr, sizeof(gr->gpr)); gr 69 arch/parisc/kernel/kgdb.c memcpy(gr->fr, regs->fr, sizeof(gr->fr)); gr 71 arch/parisc/kernel/kgdb.c gr->sr0 = regs->sr[0]; gr 72 arch/parisc/kernel/kgdb.c gr->sr1 = regs->sr[1]; gr 73 arch/parisc/kernel/kgdb.c gr->sr2 = regs->sr[2]; gr 74 arch/parisc/kernel/kgdb.c gr->sr3 = regs->sr[3]; gr 75 arch/parisc/kernel/kgdb.c gr->sr4 = regs->sr[4]; gr 76 arch/parisc/kernel/kgdb.c gr->sr5 = regs->sr[5]; gr 77 arch/parisc/kernel/kgdb.c gr->sr6 = regs->sr[6]; gr 78 arch/parisc/kernel/kgdb.c gr->sr7 = regs->sr[7]; gr 80 arch/parisc/kernel/kgdb.c gr->sar = regs->sar; gr 81 arch/parisc/kernel/kgdb.c gr->iir = regs->iir; gr 82 arch/parisc/kernel/kgdb.c gr->isr = regs->isr; gr 83 arch/parisc/kernel/kgdb.c gr->ior = regs->ior; gr 84 arch/parisc/kernel/kgdb.c gr->ipsw = regs->ipsw; gr 85 arch/parisc/kernel/kgdb.c gr->cr27 = regs->cr27; gr 87 arch/parisc/kernel/kgdb.c gr->iaoq_f = regs->iaoq[0]; gr 88 arch/parisc/kernel/kgdb.c gr->iasq_f = regs->iasq[0]; gr 90 arch/parisc/kernel/kgdb.c gr->iaoq_b = regs->iaoq[1]; gr 91 arch/parisc/kernel/kgdb.c gr->iasq_b = regs->iasq[1]; gr 96 arch/parisc/kernel/kgdb.c struct parisc_gdb_regs *gr = (struct parisc_gdb_regs *)gdb_regs; gr 99 arch/parisc/kernel/kgdb.c memcpy(regs->gr, gr->gpr, sizeof(regs->gr)); gr 100 arch/parisc/kernel/kgdb.c memcpy(regs->fr, gr->fr, sizeof(regs->fr)); gr 102 arch/parisc/kernel/kgdb.c regs->sr[0] = gr->sr0; gr 103 arch/parisc/kernel/kgdb.c regs->sr[1] = gr->sr1; gr 104 arch/parisc/kernel/kgdb.c regs->sr[2] = gr->sr2; gr 105 arch/parisc/kernel/kgdb.c regs->sr[3] = gr->sr3; gr 106 arch/parisc/kernel/kgdb.c regs->sr[4] = gr->sr4; gr 107 arch/parisc/kernel/kgdb.c regs->sr[5] = gr->sr5; gr 108 arch/parisc/kernel/kgdb.c regs->sr[6] = gr->sr6; gr 109 arch/parisc/kernel/kgdb.c regs->sr[7] = gr->sr7; gr 111 arch/parisc/kernel/kgdb.c regs->sar = gr->sar; gr 112 arch/parisc/kernel/kgdb.c regs->iir = gr->iir; gr 113 arch/parisc/kernel/kgdb.c regs->isr = gr->isr; gr 114 arch/parisc/kernel/kgdb.c regs->ior = gr->ior; gr 115 arch/parisc/kernel/kgdb.c regs->ipsw = gr->ipsw; gr 116 arch/parisc/kernel/kgdb.c regs->cr27 = gr->cr27; gr 118 arch/parisc/kernel/kgdb.c regs->iaoq[0] = gr->iaoq_f; gr 119 arch/parisc/kernel/kgdb.c regs->iasq[0] = gr->iasq_f; gr 121 arch/parisc/kernel/kgdb.c regs->iaoq[1] = gr->iaoq_b; gr 122 arch/parisc/kernel/kgdb.c regs->iasq[1] = gr->iasq_b; gr 131 arch/parisc/kernel/kgdb.c gr30 = regs->gr[30]; gr 134 arch/parisc/kernel/kgdb.c regs->gr[30] = regs->ksp; gr 138 arch/parisc/kernel/kgdb.c regs->gr[30] = gr30; gr 204 arch/parisc/kernel/kgdb.c regs->gr[0] |= PSW_R; gr 78 arch/parisc/kernel/kprobes.c regs->gr[0] |= PSW_R; gr 274 arch/parisc/kernel/kprobes.c ri->ret_addr = (kprobe_opcode_t *)regs->gr[2]; gr 277 arch/parisc/kernel/kprobes.c regs->gr[2] = (unsigned long)trampoline_p.addr; gr 238 arch/parisc/kernel/process.c cregs->gr[27] = ((unsigned long *)usp)[3]; gr 239 arch/parisc/kernel/process.c cregs->gr[26] = ((unsigned long *)usp)[2]; gr 241 arch/parisc/kernel/process.c cregs->gr[26] = usp; gr 243 arch/parisc/kernel/process.c cregs->gr[25] = kthread_arg; gr 252 arch/parisc/kernel/process.c cregs->gr[30] = usp; gr 161 arch/parisc/kernel/ptrace.c task_regs(child)->gr[0] &= ~USER_PSW_BITS; gr 162 arch/parisc/kernel/ptrace.c task_regs(child)->gr[0] |= data; gr 326 arch/parisc/kernel/ptrace.c regs->gr[28] = -ENOSYS; gr 339 arch/parisc/kernel/ptrace.c regs->gr[20] = -1UL; gr 350 arch/parisc/kernel/ptrace.c trace_sys_enter(regs, regs->gr[20]); gr 355 arch/parisc/kernel/ptrace.c audit_syscall_entry(regs->gr[20], regs->gr[26], regs->gr[25], gr 356 arch/parisc/kernel/ptrace.c regs->gr[24], regs->gr[23]); gr 359 arch/parisc/kernel/ptrace.c audit_syscall_entry(regs->gr[20] & 0xffffffff, gr 360 arch/parisc/kernel/ptrace.c regs->gr[26] & 0xffffffff, gr 361 arch/parisc/kernel/ptrace.c regs->gr[25] & 0xffffffff, gr 362 arch/parisc/kernel/ptrace.c regs->gr[24] & 0xffffffff, gr 363 arch/parisc/kernel/ptrace.c regs->gr[23] & 0xffffffff); gr 369 arch/parisc/kernel/ptrace.c return (int) ((u32) regs->gr[20]); gr 381 arch/parisc/kernel/ptrace.c trace_sys_exit(regs, regs->gr[20]); gr 458 arch/parisc/kernel/ptrace.c case RI(gr[0]) ... RI(gr[31]): return regs->gr[num - RI(gr[0])]; gr 491 arch/parisc/kernel/ptrace.c case RI(gr[0]): /* gr 499 arch/parisc/kernel/ptrace.c regs->gr[0] &= ~USER_PSW_BITS; gr 500 arch/parisc/kernel/ptrace.c regs->gr[0] |= val; gr 502 arch/parisc/kernel/ptrace.c case RI(gr[1]) ... RI(gr[31]): gr 503 arch/parisc/kernel/ptrace.c regs->gr[num - RI(gr[0])] = val; gr 715 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,0), gr 716 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,1), gr 717 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,2), gr 718 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,3), gr 719 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,4), gr 720 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,5), gr 721 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,6), gr 722 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,7), gr 723 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,8), gr 724 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,9), gr 725 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,10), gr 726 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,11), gr 727 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,12), gr 728 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,13), gr 729 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,14), gr 730 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,15), gr 731 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,16), gr 732 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,17), gr 733 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,18), gr 734 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,19), gr 735 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,20), gr 736 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,21), gr 737 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,22), gr 738 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,23), gr 739 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,24), gr 740 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,25), gr 741 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,26), gr 742 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,27), gr 743 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,28), gr 744 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,29), gr 745 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,30), gr 746 arch/parisc/kernel/ptrace.c REG_OFFSET_INDEX(gr,31), gr 76 arch/parisc/kernel/signal.c err |= __copy_from_user(regs->gr, sc->sc_gr, sizeof(regs->gr)); gr 83 arch/parisc/kernel/signal.c DBG(2,"restore_sigcontext: r28 is %ld\n", regs->gr[28]); gr 92 arch/parisc/kernel/signal.c unsigned long usp = (regs->gr[30] & ~(0x01UL)); gr 158 arch/parisc/kernel/signal.c regs->gr[31] = regs->iaoq[0]; gr 205 arch/parisc/kernel/signal.c err |= __put_user(regs->gr[31], &sc->sc_iaoq[0]); gr 206 arch/parisc/kernel/signal.c err |= __put_user(regs->gr[31]+4, &sc->sc_iaoq[1]); gr 210 arch/parisc/kernel/signal.c regs->gr[31], regs->gr[31]+4); gr 219 arch/parisc/kernel/signal.c err |= __copy_to_user(sc->sc_gr, regs->gr, sizeof(regs->gr)); gr 222 arch/parisc/kernel/signal.c DBG(1,"setup_sigcontext: r28 is %ld\n", regs->gr[28]); gr 240 arch/parisc/kernel/signal.c usp = (regs->gr[30] & ~(0x01UL)); gr 255 arch/parisc/kernel/signal.c err |= __compat_save_altstack( &compat_frame->uc.uc_stack, regs->gr[30]); gr 267 arch/parisc/kernel/signal.c err |= __save_altstack(&frame->uc.uc_stack, regs->gr[30]); gr 330 arch/parisc/kernel/signal.c regs->gr[19] = fdesc.gp; gr 343 arch/parisc/kernel/signal.c regs->gr[19] = fdesc.gp; gr 345 arch/parisc/kernel/signal.c haddr, regs->gr[19], in_syscall); gr 357 arch/parisc/kernel/signal.c regs->gr[31] = haddr; gr 381 arch/parisc/kernel/signal.c regs->gr[0] = psw; gr 386 arch/parisc/kernel/signal.c regs->gr[2] = rp; /* userland return pointer */ gr 387 arch/parisc/kernel/signal.c regs->gr[26] = ksig->sig; /* signal number */ gr 391 arch/parisc/kernel/signal.c regs->gr[25] = A(&compat_frame->info); /* siginfo pointer */ gr 392 arch/parisc/kernel/signal.c regs->gr[24] = A(&compat_frame->uc); /* ucontext pointer */ gr 396 arch/parisc/kernel/signal.c regs->gr[25] = A(&frame->info); /* siginfo pointer */ gr 397 arch/parisc/kernel/signal.c regs->gr[24] = A(&frame->uc); /* ucontext pointer */ gr 401 arch/parisc/kernel/signal.c regs->gr[30], sigframe_size, gr 402 arch/parisc/kernel/signal.c regs->gr[30] + sigframe_size); gr 404 arch/parisc/kernel/signal.c regs->gr[30] = (A(frame) + sigframe_size); gr 408 arch/parisc/kernel/signal.c current->comm, current->pid, frame, regs->gr[30], gr 434 arch/parisc/kernel/signal.c regs->gr[28]); gr 459 arch/parisc/kernel/signal.c regs->gr[31] -= 8; /* delayed branching */ gr 462 arch/parisc/kernel/signal.c uaddr = (unsigned int *) ((regs->gr[31] & ~3) + 4); gr 478 arch/parisc/kernel/signal.c regs->gr[source_reg] = regs->gr[20]; gr 493 arch/parisc/kernel/signal.c switch (regs->gr[28]) { gr 497 arch/parisc/kernel/signal.c regs->gr[28] = -EINTR; gr 503 arch/parisc/kernel/signal.c regs->gr[28] = -EINTR; gr 519 arch/parisc/kernel/signal.c switch(regs->gr[28]) { gr 522 arch/parisc/kernel/signal.c unsigned int *usp = (unsigned int *)regs->gr[30]; gr 537 arch/parisc/kernel/signal.c err |= put_user(regs->gr[31] >> 32, &usp[0]); gr 538 arch/parisc/kernel/signal.c err |= put_user(regs->gr[31] & 0xffffffff, &usp[1]); gr 541 arch/parisc/kernel/signal.c err |= put_user(regs->gr[31], &usp[0]); gr 553 arch/parisc/kernel/signal.c regs->gr[31] = regs->gr[30] + 8; gr 586 arch/parisc/kernel/signal.c DBG(3,"do_signal: signr = %d, regs->gr[28] = %ld\n", signr, regs->gr[28]); gr 600 arch/parisc/kernel/signal.c regs->gr[28]); gr 51 arch/parisc/kernel/signal32.c regs->gr[regn] = compat_reg; gr 54 arch/parisc/kernel/signal32.c regs->gr[regn] = ((u64)compat_regt << 32) | (u64)compat_reg; gr 56 arch/parisc/kernel/signal32.c regn, regs->gr[regn], compat_regt, compat_reg); gr 103 arch/parisc/kernel/signal32.c DBG(2,"restore_sigcontext32: r28 is %ld\n", regs->gr[28]); gr 133 arch/parisc/kernel/signal32.c compat_reg = (compat_uint_t)(regs->gr[31]); gr 140 arch/parisc/kernel/signal32.c compat_reg = (compat_uint_t)(regs->gr[31] >> 32); gr 145 arch/parisc/kernel/signal32.c compat_reg = (compat_uint_t)(regs->gr[31]+4); gr 150 arch/parisc/kernel/signal32.c compat_reg = (compat_uint_t)((regs->gr[31]+4) >> 32); gr 167 arch/parisc/kernel/signal32.c regs->gr[31], regs->gr[31]+4); gr 220 arch/parisc/kernel/signal32.c compat_reg = (compat_uint_t)(regs->gr[regn]); gr 223 arch/parisc/kernel/signal32.c compat_regb = (compat_uint_t)(regs->gr[regn] >> 32); gr 245 arch/parisc/kernel/signal32.c DBG(1,"setup_sigcontext32: r28 is %ld\n", regs->gr[28]); gr 128 arch/parisc/kernel/time.c if (regs->gr[0] & PSW_N) gr 133 arch/parisc/kernel/time.c pc = regs->gr[2]; gr 85 arch/parisc/kernel/traps.c printbinary(buf, regs->gr[0], 32); gr 89 arch/parisc/kernel/traps.c PRINTREGS(level, regs->gr, "r", RFMT, i); gr 152 arch/parisc/kernel/traps.c printk("%s RP(r2): " RFMT "\n", level, regs->gr[2]); gr 156 arch/parisc/kernel/traps.c printk("%s RP(r2): %pS\n", level, (void *) regs->gr[2]); gr 352 arch/parisc/kernel/traps.c regs->gr[0] = pim_wide->cr[22]; gr 355 arch/parisc/kernel/traps.c regs->gr[i] = pim_wide->gr[i]; gr 376 arch/parisc/kernel/traps.c regs->gr[0] = pim_narrow->cr[22]; gr 379 arch/parisc/kernel/traps.c regs->gr[i] = pim_narrow->gr[i]; gr 513 arch/parisc/kernel/traps.c regs->gr[0] &= ~PSW_B; gr 540 arch/parisc/kernel/traps.c regs->gr[0] &= ~PSW_R; gr 600 arch/parisc/kernel/traps.c regs->gr[regs->iir & 0x1f] = mfctl(27); gr 602 arch/parisc/kernel/traps.c regs->gr[regs->iir & 0x1f] = mfctl(26); gr 685 arch/parisc/kernel/traps.c regs->gr[0] |= PSW_X; /* So we can single-step over the trap */ gr 694 arch/parisc/kernel/traps.c regs->gr[0] &= ~PSW_T; gr 150 arch/parisc/kernel/unaligned.c regs->gr[toreg] = val; gr 190 arch/parisc/kernel/unaligned.c regs->gr[toreg] = val; gr 263 arch/parisc/kernel/unaligned.c regs->gr[toreg] = val; gr 270 arch/parisc/kernel/unaligned.c unsigned long val = regs->gr[frreg]; gr 307 arch/parisc/kernel/unaligned.c val = regs->gr[frreg]; gr 353 arch/parisc/kernel/unaligned.c val = regs->gr[frreg]; gr 438 arch/parisc/kernel/unaligned.c unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0; gr 493 arch/parisc/kernel/unaligned.c newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift; gr 495 arch/parisc/kernel/unaligned.c newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0); gr 655 arch/parisc/kernel/unaligned.c regs->gr[R1(regs->iir)] = newbase; gr 693 arch/parisc/kernel/unaligned.c regs->gr[0]|=PSW_N; gr 227 arch/parisc/kernel/unwind.c info->prev_sp = regs->gr[30]; gr 243 arch/parisc/kernel/unwind.c info->prev_sp = regs->gr[30]; gr 245 arch/parisc/kernel/unwind.c info->rp = regs->gr[2]; gr 384 arch/parisc/kernel/unwind.c info->sp = regs->gr[30]; gr 386 arch/parisc/kernel/unwind.c info->rp = regs->gr[2]; gr 387 arch/parisc/kernel/unwind.c info->r31 = regs->gr[31]; gr 402 arch/parisc/kernel/unwind.c r2->gr[30] = r->ksp; gr 425 arch/parisc/kernel/unwind.c r.gr[2] = _RET_IP_; gr 426 arch/parisc/kernel/unwind.c r.gr[30] = get_parisc_stackpointer(); gr 154 arch/parisc/mm/fault.c regs->gr[8] = -EFAULT; gr 160 arch/parisc/mm/fault.c regs->gr[treg] = 0; gr 174 arch/parisc/mm/fault.c regs->gr[0] &= ~PSW_B; /* IPSW in gr[0] */ gr 626 arch/powerpc/include/asm/smu.h __s32 gp,gr,gd; gr 347 arch/powerpc/kvm/book3s_64_mmu_hv.c unsigned long v, orig_v, gr; gr 378 arch/powerpc/kvm/book3s_64_mmu_hv.c gr = kvm->arch.hpt.rev[index].guest_rpte; gr 387 arch/powerpc/kvm/book3s_64_mmu_hv.c pp = gr & (HPTE_R_PP0 | HPTE_R_PP); gr 394 arch/powerpc/kvm/book3s_64_mmu_hv.c gpte->may_execute = gpte->may_read && !(gr & (HPTE_R_N | HPTE_R_G)); gr 398 arch/powerpc/kvm/book3s_64_mmu_hv.c int amrfield = hpte_get_skey_perm(gr, vcpu->arch.amr); gr 406 arch/powerpc/kvm/book3s_64_mmu_hv.c gpte->raddr = kvmppc_mmu_get_real_addr(v, gr, eaddr); gr 2059 arch/powerpc/kvm/book3s_64_mmu_hv.c unsigned long v, hr, gr; gr 2102 arch/powerpc/kvm/book3s_64_mmu_hv.c gr = kvm->arch.hpt.rev[i].guest_rpte; gr 2111 arch/powerpc/kvm/book3s_64_mmu_hv.c i, v, hr, gr); gr 801 arch/powerpc/kvm/book3s_hv_rm_mmu.c unsigned long v, r, gr; gr 820 arch/powerpc/kvm/book3s_hv_rm_mmu.c gr = rev->guest_rpte; gr 826 arch/powerpc/kvm/book3s_hv_rm_mmu.c gr |= r & (HPTE_R_R | HPTE_R_C); gr 829 arch/powerpc/kvm/book3s_hv_rm_mmu.c rmap = revmap_for_hpte(kvm, v, gr, NULL, NULL); gr 837 arch/powerpc/kvm/book3s_hv_rm_mmu.c vcpu->arch.regs.gpr[4] = gr; gr 849 arch/powerpc/kvm/book3s_hv_rm_mmu.c unsigned long v, r, gr; gr 867 arch/powerpc/kvm/book3s_hv_rm_mmu.c gr = rev->guest_rpte; gr 868 arch/powerpc/kvm/book3s_hv_rm_mmu.c if (gr & HPTE_R_C) { gr 877 arch/powerpc/kvm/book3s_hv_rm_mmu.c gr |= r & (HPTE_R_R | HPTE_R_C); gr 881 arch/powerpc/kvm/book3s_hv_rm_mmu.c kvmppc_set_dirty_from_hpte(kvm, v, gr); gr 884 arch/powerpc/kvm/book3s_hv_rm_mmu.c vcpu->arch.regs.gpr[4] = gr; gr 1213 arch/powerpc/kvm/book3s_hv_rm_mmu.c unsigned long v, r, gr, orig_v; gr 1232 arch/powerpc/kvm/book3s_hv_rm_mmu.c gr = cache_entry->rpte; gr 1248 arch/powerpc/kvm/book3s_hv_rm_mmu.c gr = rev->guest_rpte; gr 1258 arch/powerpc/kvm/book3s_hv_rm_mmu.c pp = gr & (HPTE_R_PP0 | HPTE_R_PP); gr 1262 arch/powerpc/kvm/book3s_hv_rm_mmu.c if (gr & (HPTE_R_N | HPTE_R_G)) gr 1277 arch/powerpc/kvm/book3s_hv_rm_mmu.c unsigned int perm = hpte_get_skey_perm(gr, vcpu->arch.amr); gr 1308 arch/powerpc/kvm/book3s_hv_rm_mmu.c cache_entry->rpte = gr; gr 65 arch/s390/include/asm/nmi.h u64 gr : 1; /* 28 general register validity */ gr 25 arch/s390/include/asm/vx-insn.h .macro GR_NUM opd gr gr 261 arch/s390/include/asm/vx-insn.h .macro VLVG v, gr, disp, m gr 269 arch/s390/include/asm/vx-insn.h .macro VLVGB v, gr, index, base gr 272 arch/s390/include/asm/vx-insn.h .macro VLVGH v, gr, index gr 275 arch/s390/include/asm/vx-insn.h .macro VLVGF v, gr, index gr 278 arch/s390/include/asm/vx-insn.h .macro VLVGG v, gr, index gr 344 arch/s390/include/asm/vx-insn.h .macro VLGV gr, vr, disp, base="%r0", m gr 352 arch/s390/include/asm/vx-insn.h .macro VLGVB gr, vr, disp, base="%r0" gr 355 arch/s390/include/asm/vx-insn.h .macro VLGVH gr, vr, disp, base="%r0" gr 358 arch/s390/include/asm/vx-insn.h .macro VLGVF gr, vr, disp, base="%r0" gr 361 arch/s390/include/asm/vx-insn.h .macro VLGVG gr, vr, disp, base="%r0" gr 198 arch/s390/kernel/nmi.c if (!mci.gr) { gr 456 arch/x86/include/asm/uv/uv_hub.h struct uv_gam_range_s *gr = uv_hub_info->gr_table; gr 460 arch/x86/include/asm/uv/uv_hub.h if (gr) { gr 461 arch/x86/include/asm/uv/uv_hub.h for (i = 0; i < num; i++, gr++) { gr 462 arch/x86/include/asm/uv/uv_hub.h if (pal < gr->limit) gr 463 arch/x86/include/asm/uv/uv_hub.h return gr; gr 466 arch/x86/include/asm/uv/uv_hub.h pr_crit("UV: GAM Range for 0x%lx not found at %p!\n", pa, gr); gr 473 arch/x86/include/asm/uv/uv_hub.h struct uv_gam_range_s *gr = uv_gam_range(pa); gr 474 arch/x86/include/asm/uv/uv_hub.h int base = gr->base; gr 226 drivers/clk/clk-gemini.c struct gemini_reset *gr = to_gemini_reset(rcdev); gr 229 drivers/clk/clk-gemini.c return regmap_write(gr->map, gr 249 drivers/clk/clk-gemini.c struct gemini_reset *gr = to_gemini_reset(rcdev); gr 253 drivers/clk/clk-gemini.c ret = regmap_read(gr->map, GEMINI_GLOBAL_SOFT_RESET, &val); gr 273 drivers/clk/clk-gemini.c struct gemini_reset *gr; gr 284 drivers/clk/clk-gemini.c gr = devm_kzalloc(dev, sizeof(*gr), GFP_KERNEL); gr 285 drivers/clk/clk-gemini.c if (!gr) gr 300 drivers/clk/clk-gemini.c gr->map = map; gr 301 drivers/clk/clk-gemini.c gr->rcdev.owner = THIS_MODULE; gr 302 drivers/clk/clk-gemini.c gr->rcdev.nr_resets = 32; gr 303 drivers/clk/clk-gemini.c gr->rcdev.ops = &gemini_reset_ops; gr 304 drivers/clk/clk-gemini.c gr->rcdev.of_node = np; gr 306 drivers/clk/clk-gemini.c ret = devm_reset_controller_register(dev, &gr->rcdev); gr 248 drivers/gpu/drm/ast/ast_drv.h u8 gr[9]; gr 276 drivers/gpu/drm/ast/ast_mode.c ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]); gr 78 drivers/gpu/drm/nouveau/include/nvif/device.h #define nvxx_gr(a) nvxx_device(a)->gr gr 164 drivers/gpu/drm/nouveau/include/nvkm/core/device.h struct nvkm_gr *gr; gr 237 drivers/gpu/drm/nouveau/include/nvkm/core/device.h int (*gr )(struct nvkm_device *, int idx, struct nvkm_gr **); gr 182 drivers/gpu/drm/nouveau/nouveau_abi16.c struct nvkm_gr *gr = nvxx_gr(device); gr 237 drivers/gpu/drm/nouveau/nouveau_abi16.c getparam->value = nvkm_gr_units(gr); gr 94 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv04_gr_new, gr 115 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv04_gr_new, gr 136 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv10_gr_new, gr 157 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv15_gr_new, gr 179 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv15_gr_new, gr 201 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv17_gr_new, gr 223 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv17_gr_new, gr 245 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv15_gr_new, gr 267 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv17_gr_new, gr 289 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv20_gr_new, gr 311 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv25_gr_new, gr 333 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv25_gr_new, gr 355 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv2a_gr_new, gr 377 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv30_gr_new, gr 399 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv30_gr_new, gr 422 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv34_gr_new, gr 445 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv35_gr_new, gr 467 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv35_gr_new, gr 492 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv40_gr_new, gr 518 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv40_gr_new, gr 544 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv40_gr_new, gr 570 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv40_gr_new, gr 596 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv44_gr_new, gr 622 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv40_gr_new, gr 648 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv44_gr_new, gr 674 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv40_gr_new, gr 700 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv40_gr_new, gr 726 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv44_gr_new, gr 752 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv40_gr_new, gr 778 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv44_gr_new, gr 804 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv44_gr_new, gr 833 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv50_gr_new, gr 859 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv44_gr_new, gr 885 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv44_gr_new, gr 911 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = nv44_gr_new, gr 942 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = g84_gr_new, gr 974 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = g84_gr_new, gr 1006 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = g84_gr_new, gr 1038 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = g84_gr_new, gr 1070 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = g84_gr_new, gr 1100 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = g84_gr_new, gr 1134 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gt200_gr_new, gr 1166 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gt215_gr_new, gr 1200 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gt215_gr_new, gr 1233 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gt215_gr_new, gr 1264 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gt200_gr_new, gr 1296 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = mcp79_gr_new, gr 1330 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = mcp89_gr_new, gr 1367 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gf100_gr_new, gr 1403 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gf108_gr_new, gr 1439 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gf104_gr_new, gr 1476 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gf104_gr_new, gr 1513 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gf110_gr_new, gr 1550 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gf104_gr_new, gr 1586 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gf104_gr_new, gr 1621 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gf117_gr_new, gr 1657 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gf119_gr_new, gr 1696 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gk104_gr_new, gr 1735 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gk104_gr_new, gr 1774 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gk104_gr_new, gr 1802 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gk20a_gr_new, gr 1838 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gk110_gr_new, gr 1876 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gk110b_gr_new, gr 1914 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gk208_gr_new, gr 1952 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gk208_gr_new, gr 1989 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gm107_gr_new, gr 2023 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gm107_gr_new, gr 2058 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gm200_gr_new, gr 2093 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gm200_gr_new, gr 2128 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gm200_gr_new, gr 2153 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gm20b_gr_new, gr 2189 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gp100_gr_new, gr 2223 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gp102_gr_new, gr 2259 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gp104_gr_new, gr 2295 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gp104_gr_new, gr 2331 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gp107_gr_new, gr 2367 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gp107_gr_new, gr 2393 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gp10b_gr_new, gr 2433 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c .gr = gv100_gr_new, gr 2698 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c _(GR , device->gr , &device->gr->engine); gr 3186 drivers/gpu/drm/nouveau/nvkm/engine/device/base.c _(NVKM_ENGINE_GR , gr); gr 31 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c struct nvkm_gr *gr = device->gr; gr 32 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c if (gr && gr->func->ctxsw.inst) gr 33 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c return gr->func->ctxsw.inst(gr); gr 40 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c struct nvkm_gr *gr = device->gr; gr 41 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c if (gr && gr->func->ctxsw.resume) gr 42 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c return gr->func->ctxsw.resume(gr); gr 49 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c struct nvkm_gr *gr = device->gr; gr 50 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c if (gr && gr->func->ctxsw.pause) gr 51 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c return gr->func->ctxsw.pause(gr); gr 58 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c struct nvkm_gr *gr = nvkm_gr(engine); gr 59 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c if (gr->func->chsw_load) gr 60 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c return gr->func->chsw_load(gr); gr 67 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c struct nvkm_gr *gr = nvkm_gr(engine); gr 68 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c if (gr->func->tile) gr 69 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c gr->func->tile(gr, region, tile); gr 73 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c nvkm_gr_units(struct nvkm_gr *gr) gr 75 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c if (gr->func->units) gr 76 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c return gr->func->units(gr); gr 81 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c nvkm_gr_tlb_flush(struct nvkm_gr *gr) gr 83 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c if (gr->func->tlb_flush) gr 84 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c return gr->func->tlb_flush(gr); gr 91 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c struct nvkm_gr *gr = nvkm_gr(oclass->engine); gr 94 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c if (gr->func->object_get) { gr 95 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c int ret = gr->func->object_get(gr, index, &oclass->base); gr 101 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c while (gr->func->sclass[c].oclass) { gr 103 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c oclass->base = gr->func->sclass[index]; gr 116 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c struct nvkm_gr *gr = nvkm_gr(oclass->engine); gr 117 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c if (gr->func->chan_new) gr 118 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c return gr->func->chan_new(gr, chan, oclass, pobject); gr 125 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c struct nvkm_gr *gr = nvkm_gr(engine); gr 126 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c gr->func->intr(gr); gr 132 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c struct nvkm_gr *gr = nvkm_gr(engine); gr 133 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c if (gr->func->oneinit) gr 134 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c return gr->func->oneinit(gr); gr 141 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c struct nvkm_gr *gr = nvkm_gr(engine); gr 142 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c return gr->func->init(gr); gr 148 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c struct nvkm_gr *gr = nvkm_gr(engine); gr 149 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c if (gr->func->fini) gr 150 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c return gr->func->fini(gr, suspend); gr 157 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c struct nvkm_gr *gr = nvkm_gr(engine); gr 158 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c if (gr->func->dtor) gr 159 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c return gr->func->dtor(gr); gr 160 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c return gr; gr 178 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c int index, bool enable, struct nvkm_gr *gr) gr 180 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c gr->func = func; gr 181 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c return nvkm_engine_ctor(&nvkm_gr, device, index, enable, &gr->engine); gr 1012 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c struct nvkm_device *device = info->gr->base.engine.subdev.device; gr 1033 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_grctx_generate_r419cb8(struct gf100_gr *gr) gr 1035 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 1042 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c const struct gf100_grctx_func *grctx = info->gr->func->grctx; gr 1054 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c const struct gf100_grctx_func *grctx = info->gr->func->grctx; gr 1066 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c struct gf100_gr *gr = info->gr; gr 1067 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c const struct gf100_grctx_func *grctx = gr->func->grctx; gr 1071 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), false); gr 1079 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gr 1080 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { gr 1090 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_grctx_generate_unkn(struct gf100_gr *gr) gr 1095 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_grctx_generate_r4060a8(struct gf100_gr *gr) gr 1097 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 1105 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c if (sm < gr->sm_nr) gr 1106 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c data |= gr->sm[sm++].gpc << (j * 8); gr 1115 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_grctx_generate_rop_mapping(struct gf100_gr *gr) gr 1117 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 1124 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c data[i / 6] |= (gr->tile[i] & 0x07) << ((i % 6) * 5); gr 1128 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c ntpcv = gr->tpc_total; gr 1141 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) | gr 1142 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gr->screen_tile_row_offset); gr 1147 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c nvkm_wr32(device, 0x419bd0, (gr->tpc_total << 8) | gr 1148 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gr->screen_tile_row_offset | data2[0]); gr 1154 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) | gr 1155 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gr->screen_tile_row_offset); gr 1161 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_grctx_generate_max_ways_evict(struct gf100_gr *gr) gr 1163 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 1271 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_grctx_generate_alpha_beta_tables(struct gf100_gr *gr) gr 1273 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 1278 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c u32 atarget = gf100_grctx_alpha_beta_map[gr->tpc_total][i]; gr 1283 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c atarget = max_t(u32, gr->tpc_total * i / 32, 1); gr 1287 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c for (gpc = 0; atarget && gpc < gr->gpc_nr; gpc++) { gr 1288 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c if (abits[gpc] < gr->tpc_nr[gpc]) { gr 1295 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gr 1296 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c u32 bbits = gr->tpc_nr[gpc] - abits[gpc]; gr 1307 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_grctx_generate_tpc_nr(struct gf100_gr *gr, int gpc) gr 1309 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 1310 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c nvkm_wr32(device, GPC_UNIT(gpc, 0x0c08), gr->tpc_nr[gpc]); gr 1311 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c nvkm_wr32(device, GPC_UNIT(gpc, 0x0c8c), gr->tpc_nr[gpc]); gr 1315 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) gr 1317 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 1325 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_grctx_generate_floorsweep(struct gf100_gr *gr) gr 1327 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 1328 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c const struct gf100_grctx_func *func = gr->func->grctx; gr 1332 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c for (sm = 0; sm < gr->sm_nr; sm++) { gr 1333 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c func->sm_id(gr, gr->sm[sm].gpc, gr->sm[sm].tpc, sm); gr 1335 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c func->tpc_nr(gr, gr->sm[sm].gpc); gr 1339 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c for (data = 0, j = 0; j < 8 && gpc < gr->gpc_nr; j++, gpc++) gr 1340 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c data |= gr->tpc_nr[gpc] << (j * 4); gr 1346 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c func->r4060a8(gr); gr 1348 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c func->rop_mapping(gr); gr 1351 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c func->alpha_beta_tables(gr); gr 1353 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c func->max_ways_evict(gr); gr 1355 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c func->dist_skip_table(gr); gr 1357 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c func->r406500(gr); gr 1359 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c func->gpc_tpc_nr(gr); gr 1361 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c func->r419f78(gr); gr 1363 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c func->tpc_mask(gr); gr 1365 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c func->smid_config(gr); gr 1369 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gr 1371 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 1372 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c const struct gf100_grctx_func *grctx = gr->func->grctx; gr 1377 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c if (!gr->fuc_sw_ctx) { gr 1378 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_gr_mmio(gr, grctx->hub); gr 1379 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_gr_mmio(gr, grctx->gpc_0); gr 1380 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_gr_mmio(gr, grctx->zcull); gr 1381 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_gr_mmio(gr, grctx->gpc_1); gr 1382 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_gr_mmio(gr, grctx->tpc); gr 1383 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_gr_mmio(gr, grctx->ppc); gr 1385 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_gr_mmio(gr, gr->fuc_sw_ctx); gr 1388 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_gr_wait_idle(gr); gr 1397 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c grctx->unkn(gr); gr 1399 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_grctx_generate_floorsweep(gr); gr 1401 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_gr_wait_idle(gr); gr 1403 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c if (grctx->r400088) grctx->r400088(gr, false); gr 1404 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c if (gr->fuc_bundle) gr 1405 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_gr_icmd(gr, gr->fuc_bundle); gr 1407 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_gr_icmd(gr, grctx->icmd); gr 1409 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_gr_icmd(gr, grctx->sw_veid_bundle_init); gr 1410 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c if (grctx->r400088) grctx->r400088(gr, true); gr 1414 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c if (gr->fuc_method) gr 1415 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_gr_mthd(gr, gr->fuc_method); gr 1417 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_gr_mthd(gr, grctx->mthd); gr 1421 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c grctx->r419cb8(gr); gr 1423 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c grctx->r418800(gr); gr 1425 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c grctx->r419eb0(gr); gr 1427 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c grctx->r419e00(gr); gr 1429 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c grctx->r418e94(gr); gr 1431 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c grctx->r419a3c(gr); gr 1433 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c grctx->r408840(gr); gr 1439 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_grctx_generate(struct gf100_gr *gr) gr 1441 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c const struct gf100_grctx_func *grctx = gr->func->grctx; gr 1442 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 1460 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c grctx->unkn88c(gr, true); gr 1470 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c grctx->unkn88c(gr, false); gr 1497 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c CB_RESERVED + gr->size, 0, true, &data); gr 1517 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c info.gr = gr; gr 1518 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c info.data = gr->mmio_data; gr 1519 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c info.mmio = gr->mmio_list; gr 1525 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c if (gr->firmware) { gr 1526 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c ret = gf100_gr_fecs_bind_pointer(gr, 0x80000000 | addr); gr 1546 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c grctx->main(gr, &info); gr 1561 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gr->data = kmalloc(gr->size, GFP_KERNEL); gr 1562 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c if (gr->data) { gr 1564 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c for (i = 0; i < gr->size; i += 4) gr 1565 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gr->data[i / 4] = nvkm_ro32(data, CB_RESERVED + i); gr 7 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h struct gf100_gr *gr; gr 738 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c struct gf100_gr *gr = info->gr; gr 739 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c const struct gf100_grctx_func *grctx = gr->func->grctx; gr 744 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), false); gr 748 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c u32 ao = bo + grctx->attrib_nr_max * gr->tpc_total; gr 756 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gr 757 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { gr 772 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c gf108_grctx_generate_unkn(struct gf100_gr *gr) gr 774 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 188 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c gf117_grctx_generate_dist_skip_table(struct gf100_gr *gr) gr 190 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 198 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c gf117_grctx_generate_rop_mapping(struct gf100_gr *gr) gr 200 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 207 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c data[i / 6] |= (gr->tile[i] & 0x07) << ((i % 6) * 5); gr 211 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c ntpcv = gr->tpc_total; gr 224 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) | gr 225 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c gr->screen_tile_row_offset); gr 230 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c nvkm_wr32(device, 0x41bfd0, (gr->tpc_total << 8) | gr 231 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c gr->screen_tile_row_offset | data2[0]); gr 237 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) | gr 238 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c gr->screen_tile_row_offset); gr 246 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c struct gf100_gr *gr = info->gr; gr 247 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c const struct gf100_grctx_func *grctx = gr->func->grctx; gr 252 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), false); gr 256 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c u32 ao = bo + grctx->attrib_nr_max * gr->tpc_total; gr 264 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gr 265 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) { gr 266 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c const u32 a = alpha * gr->ppc_tpc_nr[gpc][ppc]; gr 267 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c const u32 b = beta * gr->ppc_tpc_nr[gpc][ppc]; gr 270 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c if (!(gr->ppc_mask[gpc] & (1 << ppc))) gr 274 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; gr 276 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; gr 849 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c gk104_grctx_generate_r418800(struct gf100_gr *gr) gr 851 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 866 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c struct nvkm_device *device = info->gr->base.engine.subdev.device; gr 877 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c const struct gf100_grctx_func *grctx = info->gr->func->grctx; gr 893 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c const struct gf100_grctx_func *grctx = info->gr->func->grctx; gr 904 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c gk104_grctx_generate_unkn(struct gf100_gr *gr) gr 906 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 916 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c gk104_grctx_generate_r419f78(struct gf100_gr *gr) gr 918 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 923 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c gk104_grctx_generate_gpc_tpc_nr(struct gf100_gr *gr) gr 925 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 926 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); gr 930 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c gk104_grctx_generate_alpha_beta_tables(struct gf100_gr *gr) gr 932 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 936 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c u32 atarget = max_t(u32, gr->tpc_total * i / 32, 1); gr 937 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c u32 btarget = gr->tpc_total - atarget; gr 941 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gr 942 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c for (ppc = 0; ppc < gr->func->ppc_nr; ppc++) { gr 943 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c u32 ppc_tpcs = gr->ppc_tpc_nr[gpc][ppc]; gr 954 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c pmask = gr->ppc_tpc_mask[gpc][ppc]; gr 959 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c pmask ^= gr->ppc_tpc_mask[gpc][ppc]; gr 969 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c for (j = 0; j < gr->gpc_nr; j += 4, amask >>= 32, bmask >>= 32) { gr 817 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c gk110_grctx_generate_r419eb0(struct gf100_gr *gr) gr 819 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 28 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gr 30 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 31 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c const struct gf100_grctx_func *grctx = gr->func->grctx; gr 35 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c gf100_gr_mmio(gr, gr->fuc_sw_ctx); gr 37 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c gf100_gr_wait_idle(gr); gr 43 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c grctx->unkn(gr); gr 45 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c gf100_grctx_generate_floorsweep(gr); gr 50 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); gr 54 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c gf100_gr_wait_idle(gr); gr 57 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c gf100_gr_wait_idle(gr); gr 59 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c gf100_gr_mthd(gr, gr->fuc_method); gr 60 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c gf100_gr_wait_idle(gr); gr 62 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c gf100_gr_icmd(gr, gr->fuc_bundle); gr 869 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c gm107_grctx_generate_r419e00(struct gf100_gr *gr) gr 871 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 881 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c const struct gf100_grctx_func *grctx = info->gr->func->grctx; gr 897 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c const struct gf100_grctx_func *grctx = info->gr->func->grctx; gr 911 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c struct gf100_gr *gr = info->gr; gr 912 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c const struct gf100_grctx_func *grctx = gr->func->grctx; gr 917 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), false); gr 920 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c u32 ao = bo + grctx->attrib_nr_max * gr->tpc_total; gr 929 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gr 930 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { gr 931 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; gr 932 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc]; gr 935 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c if (!(gr->ppc_mask[gpc] & (1 << ppc))) gr 939 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; gr 942 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; gr 949 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c gm107_grctx_generate_r406500(struct gf100_gr *gr) gr 951 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c nvkm_wr32(gr->base.engine.subdev.device, 0x406500, 0x00000001); gr 955 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c gm107_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) gr 957 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 31 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c gm200_grctx_generate_r419a3c(struct gf100_gr *gr) gr 33 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 38 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c gm200_grctx_generate_r418e94(struct gf100_gr *gr) gr 40 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 46 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c gm200_grctx_generate_smid_config(struct gf100_gr *gr) gr 48 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 49 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4); gr 54 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c for (sm = 0; sm < gr->sm_nr; sm++) { gr 55 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c const u8 gpc = gr->sm[sm].gpc; gr 56 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c const u8 tpc = gr->sm[sm].tpc; gr 63 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c for (i = 0; i < gr->gpc_nr; i++) gr 68 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c gm200_grctx_generate_tpc_mask(struct gf100_gr *gr) gr 71 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c for (tmp = 0, i = 0; i < gr->gpc_nr; i++) gr 72 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * gr->func->tpc_nr); gr 73 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c nvkm_wr32(gr->base.engine.subdev.device, 0x4041c4, tmp); gr 77 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c gm200_grctx_generate_r406500(struct gf100_gr *gr) gr 79 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c nvkm_wr32(gr->base.engine.subdev.device, 0x406500, 0x00000000); gr 83 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c gm200_grctx_generate_dist_skip_table(struct gf100_gr *gr) gr 85 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 89 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gr 90 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) { gr 91 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c u8 ppc_tpcs = gr->ppc_tpc_nr[gpc][ppc]; gr 92 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c u8 ppc_tpcm = gr->ppc_tpc_mask[gpc][ppc]; gr 93 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c while (ppc_tpcs-- > gr->ppc_tpc_min) gr 95 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c ppc_tpcm ^= gr->ppc_tpc_mask[gpc][ppc]; gr 25 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gr 27 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 28 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c const struct gf100_grctx_func *grctx = gr->func->grctx; gr 32 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c gf100_gr_mmio(gr, gr->fuc_sw_ctx); gr 34 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c gf100_gr_wait_idle(gr); gr 40 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c grctx->unkn(gr); gr 42 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c gf100_grctx_generate_floorsweep(gr); gr 47 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); gr 51 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c for (tmp = 0, i = 0; i < gr->gpc_nr; i++) gr 52 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * 4); gr 55 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c gm200_grctx_generate_smid_config(gr); gr 57 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c gf100_gr_wait_idle(gr); gr 60 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c gf100_gr_wait_idle(gr); gr 62 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c gf100_gr_mthd(gr, gr->fuc_method); gr 63 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c gf100_gr_wait_idle(gr); gr 65 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c gf100_gr_icmd(gr, gr->fuc_bundle); gr 35 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c const struct gf100_grctx_func *grctx = info->gr->func->grctx; gr 47 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c struct gf100_gr *gr = info->gr; gr 48 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c const struct gf100_grctx_func *grctx = gr->func->grctx; gr 53 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c u32 size = grctx->alpha_nr_max * gr->tpc_total; gr 58 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) gr 59 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c size += grctx->attrib_nr_max * gr->ppc_nr[gpc] * gr->ppc_tpc_max; gr 72 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gr 73 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { gr 74 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; gr 75 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c const u32 bs = attrib * gr->ppc_tpc_max; gr 78 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c if (!(gr->ppc_mask[gpc] & (1 << ppc))) gr 83 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c bo += grctx->attrib_nr_max * gr->ppc_tpc_max; gr 86 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; gr 96 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c gp100_grctx_generate_smid_config(struct gf100_gr *gr) gr 98 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 99 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4); gr 103 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c for (sm = 0; sm < gr->sm_nr; sm++) { gr 104 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c const u8 gpc = gr->sm[sm].gpc; gr 105 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c const u8 tpc = gr->sm[sm].tpc; gr 107 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c gpcs[gpc + (gr->func->gpc_nr * (tpc / 4))] |= sm << ((tpc % 4) * 8); gr 33 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c gp102_grctx_generate_r408840(struct gf100_gr *gr) gr 35 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 42 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c struct gf100_gr *gr = info->gr; gr 43 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c const struct gf100_grctx_func *grctx = gr->func->grctx; gr 49 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c u32 size = grctx->alpha_nr_max * gr->tpc_total; gr 54 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) gr 55 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c size += grctx->gfxp_nr * gr->ppc_nr[gpc] * gr->ppc_tpc_max; gr 68 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gr 69 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { gr 70 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; gr 71 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c const u32 bs = attrib * gr->ppc_tpc_max; gr 72 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c const u32 gs = gfxp * gr->ppc_tpc_max; gr 76 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c if (!(gr->ppc_mask[gpc] & (1 << ppc))) gr 85 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; gr 64 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c struct gf100_gr *gr = info->gr; gr 65 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c const struct gf100_grctx_func *grctx = gr->func->grctx; gr 71 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c u32 size = grctx->alpha_nr_max * gr->tpc_total; gr 76 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c size += grctx->gfxp_nr * gr->tpc_total; gr 89 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gr 90 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { gr 91 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; gr 92 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc]; gr 93 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c const u32 gs = gfxp * gr->ppc_tpc_nr[gpc][ppc]; gr 96 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c if (!(gr->ppc_mask[gpc] & (1 << ppc))) gr 104 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; gr 114 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c gv100_grctx_generate_rop_mapping(struct gf100_gr *gr) gr 116 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 121 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) | gr 122 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c gr->screen_tile_row_offset); gr 125 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c data |= (gr->tile[i * 6 + j] & 0x1f) << (j * 5); gr 132 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c nvkm_wr32(device, 0x41bfd0, (gr->tpc_total << 8) | gr 133 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c gr->screen_tile_row_offset); gr 135 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c u8 v19 = (1 << (j + 0)) % gr->tpc_total; gr 136 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c u8 v20 = (1 << (j + 1)) % gr->tpc_total; gr 137 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c u8 v21 = (1 << (j + 2)) % gr->tpc_total; gr 138 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c u8 v22 = (1 << (j + 3)) % gr->tpc_total; gr 146 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) | gr 147 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c gr->screen_tile_row_offset); gr 151 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c gv100_grctx_generate_r400088(struct gf100_gr *gr, bool on) gr 153 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 158 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c gv100_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) gr 160 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 167 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c gv100_grctx_generate_unkn(struct gf100_gr *gr) gr 169 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 178 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c gv100_grctx_unkn88c(struct gf100_gr *gr, bool on) gr 180 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 95 drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c nvkm_gr_vstatus_print(struct nv50_gr *gr, int r, gr 98 drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 117 drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c struct nv50_gr *gr = nv50_gr(base); gr 118 drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 127 drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c spin_lock_irqsave(&gr->lock, flags); gr 158 drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c nvkm_gr_vstatus_print(gr, 0, nv50_gr_vstatus_0, gr 160 drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c nvkm_gr_vstatus_print(gr, 1, nv50_gr_vstatus_1, gr 162 drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c nvkm_gr_vstatus_print(gr, 2, nv50_gr_vstatus_2, gr 173 drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c spin_unlock_irqrestore(&gr->lock, flags); gr 49 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc) gr 51 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 52 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->zbc_color[zbc].format) { gr 53 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]); gr 54 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]); gr 55 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]); gr 56 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]); gr 58 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format); gr 64 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_zbc_color_get(struct gf100_gr *gr, int format, gr 67 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; gr 71 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->zbc_color[i].format) { gr 72 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->zbc_color[i].format != format) gr 74 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (memcmp(gr->zbc_color[i].ds, ds, sizeof( gr 75 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->zbc_color[i].ds))) gr 77 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (memcmp(gr->zbc_color[i].l2, l2, sizeof( gr 78 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->zbc_color[i].l2))) { gr 91 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c memcpy(gr->zbc_color[zbc].ds, ds, sizeof(gr->zbc_color[zbc].ds)); gr 92 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2)); gr 93 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->zbc_color[zbc].format = format; gr 95 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->zbc->clear_color(gr, zbc); gr 100 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc) gr 102 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 103 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->zbc_depth[zbc].format) gr 104 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds); gr 105 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format); gr 111 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format, gr 114 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; gr 118 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->zbc_depth[i].format) { gr 119 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->zbc_depth[i].format != format) gr 121 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->zbc_depth[i].ds != ds) gr 123 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->zbc_depth[i].l2 != l2) { gr 136 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->zbc_depth[zbc].format = format; gr 137 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->zbc_depth[zbc].ds = ds; gr 138 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->zbc_depth[zbc].l2 = l2; gr 140 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->zbc->clear_depth(gr, zbc); gr 163 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine)); gr 190 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c ret = gf100_gr_zbc_color_get(gr, args->v0.format, gr 209 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine)); gr 218 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c ret = gf100_gr_zbc_depth_get(gr, args->v0.format, gr 301 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr *gr = gf100_gr(base); gr 304 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c while (gr->func->sclass[c].oclass) { gr 306 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c *sclass = gr->func->sclass[index]; gr 324 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr *gr = chan->gr; gr 327 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size, gr 333 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (i = 0; i < gr->size; i += 4) gr 334 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wo32(*pgpuobj, i, gr->data[i / 4]); gr 336 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (!gr->firmware) { gr 382 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr *gr = gf100_gr(base); gr 383 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr_data *data = gr->mmio_data; gr 384 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr_mmio *mmio = gr->mmio_list; gr 387 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 393 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c chan->gr = gr; gr 416 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (i = 0; data->size && i < ARRAY_SIZE(gr->mmio_data); i++) { gr 441 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (i = 0; mmio->addr && i < ARRAY_SIZE(gr->mmio_list); i++) { gr 719 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_ctxsw_inst(struct nvkm_gr *gr) gr 721 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c return nvkm_rd32(gr->engine.subdev.device, 0x409b00); gr 725 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_fecs_ctrl_ctxsw(struct gf100_gr *gr, u32 mthd) gr 727 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 747 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr *gr = gf100_gr(base); gr 750 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c mutex_lock(&gr->fecs.mutex); gr 751 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (!--gr->fecs.disable) { gr 752 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (WARN_ON(ret = gf100_gr_fecs_ctrl_ctxsw(gr, 0x39))) gr 753 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->fecs.disable++; gr 755 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c mutex_unlock(&gr->fecs.mutex); gr 762 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr *gr = gf100_gr(base); gr 765 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c mutex_lock(&gr->fecs.mutex); gr 766 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (!gr->fecs.disable++) { gr 767 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (WARN_ON(ret = gf100_gr_fecs_ctrl_ctxsw(gr, 0x38))) gr 768 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->fecs.disable--; gr 770 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c mutex_unlock(&gr->fecs.mutex); gr 775 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_fecs_bind_pointer(struct gf100_gr *gr, u32 inst) gr 777 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 794 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_fecs_set_reglist_virtual_address(struct gf100_gr *gr, u64 addr) gr 796 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 811 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_fecs_set_reglist_bind_instance(struct gf100_gr *gr, u32 inst) gr 813 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 828 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_fecs_discover_reglist_image_size(struct gf100_gr *gr, u32 *psize) gr 830 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 844 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_fecs_elpg_bind(struct gf100_gr *gr) gr 849 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c ret = gf100_gr_fecs_discover_reglist_image_size(gr, &size); gr 858 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c ret = gf100_gr_fecs_set_reglist_bind_instance(gr, 0); gr 862 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c return gf100_gr_fecs_set_reglist_virtual_address(gr, 0); gr 866 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_fecs_discover_pm_image_size(struct gf100_gr *gr, u32 *psize) gr 868 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 882 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_fecs_discover_zcull_image_size(struct gf100_gr *gr, u32 *psize) gr 884 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 898 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_fecs_discover_image_size(struct gf100_gr *gr, u32 *psize) gr 900 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 914 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_fecs_set_watchdog_timeout(struct gf100_gr *gr, u32 timeout) gr 916 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 926 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr *gr = gf100_gr(base); gr 927 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (!gr->firmware) { gr 928 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 trace = nvkm_rd32(gr->base.engine.subdev.device, 0x40981c); gr 932 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 mthd = nvkm_rd32(gr->base.engine.subdev.device, 0x409808); gr 940 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_rops(struct gf100_gr *gr) gr 942 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 947 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_zbc_init(struct gf100_gr *gr) gr 957 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; gr 960 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (!gr->zbc_color[0].format) { gr 961 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_zbc_color_get(gr, 1, & zero[0], &zero[4]); c++; gr 962 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_zbc_color_get(gr, 2, & one[0], &one[4]); c++; gr 963 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_zbc_color_get(gr, 4, &f32_0[0], &f32_0[4]); c++; gr 964 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_zbc_color_get(gr, 4, &f32_1[0], &f32_1[4]); c++; gr 965 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_zbc_depth_get(gr, 1, 0x00000000, 0x00000000); d++; gr 966 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_zbc_depth_get(gr, 1, 0x3f800000, 0x3f800000); d++; gr 967 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->func->zbc->stencil_get) { gr 968 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->zbc->stencil_get(gr, 1, 0x00, 0x00); s++; gr 969 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->zbc->stencil_get(gr, 1, 0x01, 0x01); s++; gr 970 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->zbc->stencil_get(gr, 1, 0xff, 0xff); s++; gr 975 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->zbc->clear_color(gr, index); gr 977 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->zbc->clear_depth(gr, index); gr 979 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->func->zbc->clear_stencil) { gr 981 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->zbc->clear_stencil(gr, index); gr 991 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_wait_idle(struct gf100_gr *gr) gr 993 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 1020 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_mmio(struct gf100_gr *gr, const struct gf100_gr_pack *p) gr 1022 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 1037 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_icmd(struct gf100_gr *gr, const struct gf100_gr_pack *p) gr 1039 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 1062 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_wait_idle(gr); gr 1075 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_mthd(struct gf100_gr *gr, const struct gf100_gr_pack *p) gr 1077 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 1102 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr *gr = gf100_gr(base); gr 1105 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c cfg = (u32)gr->gpc_nr; gr 1106 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c cfg |= (u32)gr->tpc_total << 8; gr 1107 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c cfg |= (u64)gr->rop_nr << 32; gr 1174 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc) gr 1176 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 1235 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) gr 1237 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 1256 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc) gr 1258 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 1270 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->trap_mp(gr, gpc, tpc); gr 1301 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc) gr 1303 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 1309 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_trap_gpc_rop(gr, gpc); gr 1334 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { gr 1337 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_trap_tpc(gr, gpc, tpc); gr 1349 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_trap_intr(struct gf100_gr *gr) gr 1351 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 1443 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (gpc = 0; stat && gpc < gr->gpc_nr; gpc++) { gr 1446 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_trap_gpc(gr, gpc); gr 1456 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (rop = 0; rop < gr->rop_nr; rop++) { gr 1475 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_ctxctl_debug_unit(struct gf100_gr *gr, u32 base) gr 1477 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 1494 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_ctxctl_debug(struct gf100_gr *gr) gr 1496 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 1500 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_ctxctl_debug_unit(gr, 0x409000); gr 1502 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_ctxctl_debug_unit(gr, 0x502000 + (gpc * 0x8000)); gr 1506 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_ctxctl_isr(struct gf100_gr *gr) gr 1508 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 1512 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (!gr->firmware && (stat & 0x00000001)) { gr 1531 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (!gr->firmware && (stat & 0x00080000)) { gr 1533 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_ctxctl_debug(gr); gr 1540 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_ctxctl_debug(gr); gr 1548 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr *gr = gf100_gr(base); gr 1549 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 1617 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_trap_intr(gr); gr 1623 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_ctxctl_isr(gr); gr 1646 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init_csdata(struct gf100_gr *gr, gr 1650 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 1689 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init_ctxctl_ext(struct gf100_gr *gr) gr 1691 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 1704 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init_fw(gr->fecs.falcon, &gr->fuc409c, &gr->fuc409d); gr 1709 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init_fw(gr->gpccs.falcon, &gr->fuc41ac, &gr->fuc41ad); gr 1724 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_falcon_start(gr->gpccs.falcon); gr 1725 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_falcon_start(gr->fecs.falcon); gr 1733 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_fecs_set_watchdog_timeout(gr, 0x7fffffff); gr 1736 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c ret = gf100_gr_fecs_discover_image_size(gr, &gr->size); gr 1741 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c ret = gf100_gr_fecs_discover_zcull_image_size(gr, &gr->size_zcull); gr 1746 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c ret = gf100_gr_fecs_discover_pm_image_size(gr, &gr->size_pm); gr 1757 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c ret = gf100_gr_fecs_elpg_bind(gr); gr 1763 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->data == NULL) { gr 1764 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c int ret = gf100_grctx_generate(gr); gr 1775 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init_ctxctl_int(struct gf100_gr *gr) gr 1777 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c const struct gf100_grctx_func *grctx = gr->func->grctx; gr 1778 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 1781 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (!gr->func->fecs.ucode) { gr 1787 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_falcon_load_dmem(gr->fecs.falcon, gr 1788 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->fecs.ucode->data.data, 0x0, gr 1789 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->fecs.ucode->data.size, 0); gr 1790 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_falcon_load_imem(gr->fecs.falcon, gr 1791 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->fecs.ucode->code.data, 0x0, gr 1792 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->fecs.ucode->code.size, 0, 0, false); gr 1795 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_falcon_load_dmem(gr->gpccs.falcon, gr 1796 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->gpccs.ucode->data.data, 0x0, gr 1797 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->gpccs.ucode->data.size, 0); gr 1798 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_falcon_load_imem(gr->gpccs.falcon, gr 1799 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->gpccs.ucode->code.data, 0x0, gr 1800 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->gpccs.ucode->code.size, 0, 0, false); gr 1804 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init_csdata(gr, grctx->hub, 0x409000, 0x000, 0x000000); gr 1805 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init_csdata(gr, grctx->gpc_0, 0x41a000, 0x000, 0x418000); gr 1806 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init_csdata(gr, grctx->gpc_1, 0x41a000, 0x000, 0x418000); gr 1807 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init_csdata(gr, grctx->tpc, 0x41a000, 0x004, 0x419800); gr 1808 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init_csdata(gr, grctx->ppc, 0x41a000, 0x008, 0x41be00); gr 1817 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_ctxctl_debug(gr); gr 1821 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->size = nvkm_rd32(device, 0x409804); gr 1822 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->data == NULL) { gr 1823 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c int ret = gf100_grctx_generate(gr); gr 1834 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init_ctxctl(struct gf100_gr *gr) gr 1838 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->firmware) gr 1839 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c ret = gf100_gr_init_ctxctl_ext(gr); gr 1841 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c ret = gf100_gr_init_ctxctl_int(gr); gr 1847 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_oneinit_sm_id(struct gf100_gr *gr) gr 1850 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (tpc = 0; tpc < gr->tpc_max; tpc++) { gr 1851 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gr 1852 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (tpc < gr->tpc_nr[gpc]) { gr 1853 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->sm[gr->sm_nr].gpc = gpc; gr 1854 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->sm[gr->sm_nr].tpc = tpc; gr 1855 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->sm_nr++; gr 1862 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_oneinit_tiles(struct gf100_gr *gr) gr 1872 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c switch (gr->tpc_total) { gr 1873 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c case 15: gr->screen_tile_row_offset = 0x06; break; gr 1874 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c case 14: gr->screen_tile_row_offset = 0x05; break; gr 1875 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c case 13: gr->screen_tile_row_offset = 0x02; break; gr 1876 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c case 11: gr->screen_tile_row_offset = 0x07; break; gr 1877 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c case 10: gr->screen_tile_row_offset = 0x06; break; gr 1879 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c case 5: gr->screen_tile_row_offset = 0x01; break; gr 1880 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c case 3: gr->screen_tile_row_offset = 0x02; break; gr 1882 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c case 1: gr->screen_tile_row_offset = 0x01; break; gr 1883 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c default: gr->screen_tile_row_offset = 0x03; gr 1885 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->tpc_total % primes[i]) { gr 1886 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->screen_tile_row_offset = primes[i]; gr 1894 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (i = 0; i < gr->gpc_nr; i++) gr 1899 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (sorted = true, i = 0; i < gr->gpc_nr - 1; i++) { gr 1900 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->tpc_nr[gpc_map[i + 1]] > gr 1901 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->tpc_nr[gpc_map[i + 0]]) { gr 1911 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c mul_factor = gr->gpc_nr * gr->tpc_max; gr 1917 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c comm_denom = gr->gpc_nr * gr->tpc_max * mul_factor; gr 1919 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (i = 0; i < gr->gpc_nr; i++) { gr 1920 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c init_frac[i] = gr->tpc_nr[gpc_map[i]] * gr->gpc_nr * mul_factor; gr 1921 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c init_err[i] = i * gr->tpc_max * mul_factor - comm_denom/2; gr 1925 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (i = 0; i < gr->tpc_total;) { gr 1926 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (j = 0; j < gr->gpc_nr; j++) { gr 1928 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->tile[i++] = gpc_map[j]; gr 1940 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr *gr = gf100_gr(base); gr 1941 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 1946 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c ret = nvkm_falcon_v1_new(subdev, "FECS", 0x409000, &gr->fecs.falcon); gr 1950 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c mutex_init(&gr->fecs.mutex); gr 1952 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c ret = nvkm_falcon_v1_new(subdev, "GPCCS", 0x41a000, &gr->gpccs.falcon); gr 1958 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->rop_nr = gr->func->rops(gr); gr 1959 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f; gr 1960 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (i = 0; i < gr->gpc_nr; i++) { gr 1961 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->tpc_nr[i] = nvkm_rd32(device, GPC_UNIT(i, 0x2608)); gr 1962 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->tpc_max = max(gr->tpc_max, gr->tpc_nr[i]); gr 1963 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->tpc_total += gr->tpc_nr[i]; gr 1964 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->ppc_nr[i] = gr->func->ppc_nr; gr 1965 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (j = 0; j < gr->ppc_nr[i]; j++) { gr 1966 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->ppc_tpc_mask[i][j] = gr 1968 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->ppc_tpc_mask[i][j] == 0) gr 1970 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->ppc_mask[i] |= (1 << j); gr 1971 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->ppc_tpc_nr[i][j] = hweight8(gr->ppc_tpc_mask[i][j]); gr 1972 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->ppc_tpc_min == 0 || gr 1973 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->ppc_tpc_min > gr->ppc_tpc_nr[i][j]) gr 1974 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->ppc_tpc_min = gr->ppc_tpc_nr[i][j]; gr 1975 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->ppc_tpc_max < gr->ppc_tpc_nr[i][j]) gr 1976 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->ppc_tpc_max = gr->ppc_tpc_nr[i][j]; gr 1980 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c memset(gr->tile, 0xff, sizeof(gr->tile)); gr 1981 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->oneinit_tiles(gr); gr 1982 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->oneinit_sm_id(gr); gr 1989 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr *gr = gf100_gr(base); gr 2019 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_pmu_pgob(gr->base.engine.subdev.device->pmu, false); gr 2021 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c ret = nvkm_falcon_get(gr->fecs.falcon, subdev); gr 2025 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c ret = nvkm_falcon_get(gr->gpccs.falcon, subdev); gr 2029 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c return gr->func->init(gr); gr 2035 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr *gr = gf100_gr(base); gr 2036 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 2037 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_falcon_put(gr->gpccs.falcon, subdev); gr 2038 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_falcon_put(gr->fecs.falcon, subdev); gr 2058 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr *gr = gf100_gr(base); gr 2060 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->func->dtor) gr 2061 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->dtor(gr); gr 2062 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c kfree(gr->data); gr 2064 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_falcon_del(&gr->gpccs.falcon); gr 2065 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_falcon_del(&gr->fecs.falcon); gr 2067 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_dtor_fw(&gr->fuc409c); gr 2068 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_dtor_fw(&gr->fuc409d); gr 2069 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_dtor_fw(&gr->fuc41ac); gr 2070 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_dtor_fw(&gr->fuc41ad); gr 2072 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_dtor_init(gr->fuc_bundle); gr 2073 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_dtor_init(gr->fuc_method); gr 2074 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_dtor_init(gr->fuc_sw_ctx); gr 2075 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_dtor_init(gr->fuc_sw_nonctx); gr 2077 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c return gr; gr 2097 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_ctor_fw_legacy(struct gf100_gr *gr, const char *fwname, gr 2100 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 2141 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname, gr 2147 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c ret = nvkm_firmware_get(&gr->base.engine.subdev, fwname, &fw); gr 2149 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c ret = gf100_gr_ctor_fw_legacy(gr, fwname, fuc, ret); gr 2163 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c int index, struct gf100_gr *gr) gr 2165 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func = func; gr 2166 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->firmware = nvkm_boolopt(device->cfgopt, "NvGrUseFW", gr 2170 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->firmware || func->fecs.ucode != NULL, gr 2171 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c &gr->base); gr 2178 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct gf100_gr *gr; gr 2181 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL))) gr 2183 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c *pgr = &gr->base; gr 2185 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c ret = gf100_gr_ctor(func, device, index, gr); gr 2189 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->firmware) { gr 2190 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) || gr 2191 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) || gr 2192 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) || gr 2193 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad)) gr 2201 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init_400054(struct gf100_gr *gr) gr 2203 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(gr->base.engine.subdev.device, 0x400054, 0x34ce3464); gr 2207 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) gr 2209 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 2215 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init_tex_hww_esr(struct gf100_gr *gr, int gpc, int tpc) gr 2217 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 2222 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init_419eb4(struct gf100_gr *gr) gr 2224 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 2229 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init_419cc0(struct gf100_gr *gr) gr 2231 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 2236 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gr 2237 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) gr 2243 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init_40601c(struct gf100_gr *gr) gr 2245 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(gr->base.engine.subdev.device, 0x40601c, 0xc0000000); gr 2249 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init_fecs_exceptions(struct gf100_gr *gr) gr 2251 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c const u32 data = gr->firmware ? 0x000e0000 : 0x000e0001; gr 2252 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, data); gr 2256 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init_gpc_mmu(struct gf100_gr *gr) gr 2258 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 2272 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init_num_active_ltcs(struct gf100_gr *gr) gr 2274 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 2279 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init_zcull(struct gf100_gr *gr) gr 2281 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 2282 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); gr 2283 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c const u8 tile_nr = ALIGN(gr->tpc_total, 32); gr 2288 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) { gr 2289 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c data |= bank[gr->tile[i + j]] << (j * 4); gr 2290 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c bank[gr->tile[i + j]]++; gr 2295 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gr 2297 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); gr 2299 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->tpc_total); gr 2307 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init_vsc_stream_master(struct gf100_gr *gr) gr 2309 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 2314 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init(struct gf100_gr *gr) gr 2316 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 2319 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->func->init_419bd8) gr 2320 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->init_419bd8(gr); gr 2322 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->init_gpc_mmu(gr); gr 2324 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->fuc_sw_nonctx) gr 2325 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_mmio(gr, gr->fuc_sw_nonctx); gr 2327 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_mmio(gr, gr->func->mmio); gr 2329 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_wait_idle(gr); gr 2331 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->func->init_r405a14) gr 2332 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->init_r405a14(gr); gr 2334 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->func->clkgate_pack) gr 2335 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_therm_clkgate_init(device->therm, gr->func->clkgate_pack); gr 2337 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->func->init_bios) gr 2338 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->init_bios(gr); gr 2340 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->init_vsc_stream_master(gr); gr 2341 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->init_zcull(gr); gr 2342 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->init_num_active_ltcs(gr); gr 2343 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->func->init_rop_active_fbps) gr 2344 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->init_rop_active_fbps(gr); gr 2345 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->func->init_bios_2) gr 2346 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->init_bios_2(gr); gr 2347 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->func->init_swdx_pes_mask) gr 2348 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->init_swdx_pes_mask(gr); gr 2356 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->init_fecs_exceptions(gr); gr 2357 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->func->init_ds_hww_esr_2) gr 2358 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->init_ds_hww_esr_2(gr); gr 2364 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->func->init_40601c) gr 2365 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->init_40601c(gr); gr 2370 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->func->init_sked_hww_esr) gr 2371 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->init_sked_hww_esr(gr); gr 2376 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->func->init_419cc0) gr 2377 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->init_419cc0(gr); gr 2378 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->func->init_419eb4) gr 2379 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->init_419eb4(gr); gr 2380 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->func->init_419c9c) gr 2381 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->init_419c9c(gr); gr 2383 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->func->init_ppc_exceptions) gr 2384 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->init_ppc_exceptions(gr); gr 2386 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gr 2391 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { gr 2394 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->func->init_tex_hww_esr) gr 2395 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->init_tex_hww_esr(gr, gpc, tpc); gr 2397 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->func->init_504430) gr 2398 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->init_504430(gr, gpc, tpc); gr 2399 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->init_shader_exceptions(gr, gpc, tpc); gr 2405 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (rop = 0; rop < gr->rop_nr; rop++) { gr 2419 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->func->init_400054) gr 2420 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->init_400054(gr); gr 2422 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_zbc_init(gr); gr 2424 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->func->init_4188a4) gr 2425 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->init_4188a4(gr); gr 2427 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c return gf100_gr_init_ctxctl(gr); gr 257 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h struct gf100_gr *gr; gr 107 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c gf108_gr_init_r405a14(struct gf100_gr *gr) gr 109 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c nvkm_wr32(gr->base.engine.subdev.device, 0x405a14, 0x80000000); gr 124 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c gf117_gr_init_zcull(struct gf100_gr *gr) gr 126 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 127 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); gr 128 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c const u8 tile_nr = ALIGN(gr->tpc_total, 32); gr 133 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) { gr 134 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c data |= bank[gr->tile[i + j]] << (j * 4); gr 135 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c bank[gr->tile[i + j]]++; gr 140 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gr 142 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); gr 144 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c gr->tpc_total); gr 391 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c gk104_gr_init_sked_hww_esr(struct gf100_gr *gr) gr 393 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c nvkm_wr32(gr->base.engine.subdev.device, 0x407020, 0x40000000); gr 397 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c gk104_gr_init_fecs_exceptions(struct gf100_gr *gr) gr 399 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 406 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c gk104_gr_init_rop_active_fbps(struct gf100_gr *gr) gr 408 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 415 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c gk104_gr_init_ppc_exceptions(struct gf100_gr *gr) gr 417 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 420 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gr 421 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) { gr 422 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c if (!(gr->ppc_mask[gpc] & (1 << ppc))) gr 430 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c gk104_gr_init_vsc_stream_master(struct gf100_gr *gr) gr 432 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 339 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c gk110_gr_init_419eb4(struct gf100_gr *gr) gr 341 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 36 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c gk20a_gr_av_to_init(struct gf100_gr *gr, const char *fw_name, gr 46 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c ret = gf100_gr_ctor_fw(gr, fw_name, &fuc); gr 85 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c gk20a_gr_aiv_to_init(struct gf100_gr *gr, const char *fw_name, gr 95 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c ret = gf100_gr_ctor_fw(gr, fw_name, &fuc); gr 127 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c gk20a_gr_av_to_method(struct gf100_gr *gr, const char *fw_name, gr 140 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c ret = gf100_gr_ctor_fw(gr, fw_name, &fuc); gr 187 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c gk20a_gr_wait_mem_scrubbing(struct gf100_gr *gr) gr 189 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 212 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c gk20a_gr_set_hww_esr_report_mask(struct gf100_gr *gr) gr 214 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 220 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c gk20a_gr_init(struct gf100_gr *gr) gr 222 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 228 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c gf100_gr_mmio(gr, gr->fuc_sw_nonctx); gr 230 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c ret = gk20a_gr_wait_mem_scrubbing(gr); gr 234 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c ret = gf100_gr_wait_idle(gr); gr 239 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c if (gr->func->init_gpc_mmu) gr 240 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c gr->func->init_gpc_mmu(gr); gr 246 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c gr->func->init_zcull(gr); gr 248 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c gr->func->init_rop_active_fbps(gr); gr 264 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c if (gr->func->set_hww_esr_report_mask) gr 265 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c gr->func->set_hww_esr_report_mask(gr); gr 269 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c nvkm_wr32(device, 0x41ac94, (((1 << gr->tpc_total) - 1) & 0xff) << 16); gr 279 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c gf100_gr_zbc_init(gr); gr 281 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c return gf100_gr_init_ctxctl(gr); gr 309 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c struct gf100_gr *gr; gr 312 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL))) gr 314 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c *pgr = &gr->base; gr 316 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c ret = gf100_gr_ctor(&gk20a_gr, device, index, gr); gr 320 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) || gr 321 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) || gr 322 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) || gr 323 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad)) gr 326 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c ret = gk20a_gr_av_to_init(gr, "sw_nonctx", &gr->fuc_sw_nonctx); gr 330 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c ret = gk20a_gr_aiv_to_init(gr, "sw_ctx", &gr->fuc_sw_ctx); gr 334 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c ret = gk20a_gr_av_to_init(gr, "sw_bundle_init", &gr->fuc_bundle); gr 338 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c ret = gk20a_gr_av_to_method(gr, "sw_method_init", &gr->fuc_method); gr 288 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c gm107_gr_init_400054(struct gf100_gr *gr) gr 290 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c nvkm_wr32(gr->base.engine.subdev.device, 0x400054, 0x2c350f63); gr 294 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c gm107_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) gr 296 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 302 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c gm107_gr_init_504430(struct gf100_gr *gr, int gpc, int tpc) gr 304 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 309 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c gm107_gr_init_bios_2(struct gf100_gr *gr) gr 311 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 334 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c gm107_gr_init_bios(struct gf100_gr *gr) gr 346 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 363 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c gm107_gr_init_gpc_mmu(struct gf100_gr *gr) gr 365 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 36 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c gm200_gr_rops(struct gf100_gr *gr) gr 38 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c return nvkm_rd32(gr->base.engine.subdev.device, 0x12006c); gr 42 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c gm200_gr_init_ds_hww_esr_2(struct gf100_gr *gr) gr 44 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 50 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c gm200_gr_init_num_active_ltcs(struct gf100_gr *gr) gr 52 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 58 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c gm200_gr_init_gpc_mmu(struct gf100_gr *gr) gr 60 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 72 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c gm200_gr_init_rop_active_fbps(struct gf100_gr *gr) gr 74 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 96 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c gm200_gr_oneinit_sm_id(struct gf100_gr *gr) gr 99 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c gf100_gr_oneinit_sm_id(gr); gr 103 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c gm200_gr_oneinit_tiles(struct gf100_gr *gr) gr 111 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c if (gr->gpc_nr == 2 && gr->tpc_total == 8) { gr 112 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c memcpy(gr->tile, gm200_gr_tile_map_2_8, gr->tpc_total); gr 113 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c gr->screen_tile_row_offset = 1; gr 115 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c if (gr->gpc_nr == 4 && gr->tpc_total == 16) { gr 116 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c memcpy(gr->tile, gm200_gr_tile_map_4_16, gr->tpc_total); gr 117 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c gr->screen_tile_row_offset = 4; gr 119 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c if (gr->gpc_nr == 6 && gr->tpc_total == 24) { gr 120 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c memcpy(gr->tile, gm200_gr_tile_map_6_24, gr->tpc_total); gr 121 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c gr->screen_tile_row_offset = 5; gr 123 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c gf100_gr_oneinit_tiles(gr); gr 131 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c struct gf100_gr *gr; gr 134 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL))) gr 136 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c *pgr = &gr->base; gr 138 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c ret = gf100_gr_ctor(func, device, index, gr); gr 145 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c if ((ret = gf100_gr_ctor_fw(gr, "gr/fecs_inst", &gr->fuc409c)) || gr 146 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c (ret = gf100_gr_ctor_fw(gr, "gr/fecs_data", &gr->fuc409d))) gr 151 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c if ((ret = gf100_gr_ctor_fw(gr, "gr/gpccs_inst", &gr->fuc41ac)) || gr 152 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c (ret = gf100_gr_ctor_fw(gr, "gr/gpccs_data", &gr->fuc41ad))) gr 156 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c if ((ret = gk20a_gr_av_to_init(gr, "gr/sw_nonctx", &gr->fuc_sw_nonctx)) || gr 157 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c (ret = gk20a_gr_aiv_to_init(gr, "gr/sw_ctx", &gr->fuc_sw_ctx)) || gr 158 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c (ret = gk20a_gr_av_to_init(gr, "gr/sw_bundle_init", &gr->fuc_bundle)) || gr 159 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c (ret = gk20a_gr_av_to_method(gr, "gr/sw_method_init", &gr->fuc_method))) gr 30 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c gm20b_gr_init_gpc_mmu(struct gf100_gr *gr) gr 32 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 58 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c gm20b_gr_set_hww_esr_report_mask(struct gf100_gr *gr) gr 60 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 33 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c gp100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc) gr 35 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 39 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c if (gr->zbc_color[zbc].format) { gr 40 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c nvkm_wr32(device, 0x418010 + zoff, gr->zbc_color[zbc].ds[0]); gr 41 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c nvkm_wr32(device, 0x41804c + zoff, gr->zbc_color[zbc].ds[1]); gr 42 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c nvkm_wr32(device, 0x418088 + zoff, gr->zbc_color[zbc].ds[2]); gr 43 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c nvkm_wr32(device, 0x4180c4 + zoff, gr->zbc_color[zbc].ds[3]); gr 48 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c gr->zbc_color[zbc].format << ((znum % 4) * 7)); gr 52 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c gp100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc) gr 54 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 58 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c if (gr->zbc_depth[zbc].format) gr 59 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c nvkm_wr32(device, 0x418110 + zoff, gr->zbc_depth[zbc].ds); gr 62 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c gr->zbc_depth[zbc].format << ((znum % 4) * 7)); gr 72 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c gp100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) gr 74 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 80 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c gp100_gr_init_419c9c(struct gf100_gr *gr) gr 82 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 88 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c gp100_gr_init_fecs_exceptions(struct gf100_gr *gr) gr 90 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, 0x000f0002); gr 94 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c gp100_gr_init_rop_active_fbps(struct gf100_gr *gr) gr 96 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 30 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c gp102_gr_zbc_clear_stencil(struct gf100_gr *gr, int zbc) gr 32 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 36 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c if (gr->zbc_stencil[zbc].format) gr 37 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c nvkm_wr32(device, 0x41815c + zoff, gr->zbc_stencil[zbc].ds); gr 40 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c gr->zbc_stencil[zbc].format << ((znum % 4) * 7)); gr 44 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c gp102_gr_zbc_stencil_get(struct gf100_gr *gr, int format, gr 47 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; gr 51 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c if (gr->zbc_stencil[i].format) { gr 52 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c if (gr->zbc_stencil[i].format != format) gr 54 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c if (gr->zbc_stencil[i].ds != ds) gr 56 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c if (gr->zbc_stencil[i].l2 != l2) { gr 69 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c gr->zbc_stencil[zbc].format = format; gr 70 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c gr->zbc_stencil[zbc].ds = ds; gr 71 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c gr->zbc_stencil[zbc].l2 = l2; gr 73 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c gr->func->zbc->clear_stencil(gr, zbc); gr 86 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c gp102_gr_init_swdx_pes_mask(struct gf100_gr *gr) gr 88 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 91 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gr 28 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c gv100_gr_trap_sm(struct gf100_gr *gr, int gpc, int tpc, int sm) gr 30 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 49 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c gv100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) gr 51 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c gv100_gr_trap_sm(gr, gpc, tpc, 0); gr 52 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c gv100_gr_trap_sm(gr, gpc, tpc, 1); gr 56 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c gv100_gr_init_4188a4(struct gf100_gr *gr) gr 58 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 63 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c gv100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) gr 65 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 75 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c gv100_gr_init_504430(struct gf100_gr *gr, int gpc, int tpc) gr 77 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 82 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c gv100_gr_init_419bd8(struct gf100_gr *gr) gr 84 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 361 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c struct nv04_gr *gr; gr 1072 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nv04_gr_channel(struct nv04_gr *gr) gr 1074 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 1078 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c if (chid < ARRAY_SIZE(gr->chan)) gr 1079 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c chan = gr->chan[chid]; gr 1087 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c struct nvkm_device *device = chan->gr->base.engine.subdev.device; gr 1102 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c struct nvkm_device *device = chan->gr->base.engine.subdev.device; gr 1114 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nv04_gr_context_switch(struct nv04_gr *gr) gr 1116 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 1121 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nv04_gr_idle(&gr->base); gr 1124 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c prev = nv04_gr_channel(gr); gr 1130 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c next = gr->chan[chid]; gr 1151 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c struct nv04_gr *gr = chan->gr; gr 1154 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c spin_lock_irqsave(&gr->lock, flags); gr 1155 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c gr->chan[chan->chid] = NULL; gr 1156 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c spin_unlock_irqrestore(&gr->lock, flags); gr 1164 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c struct nv04_gr *gr = chan->gr; gr 1165 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 1168 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c spin_lock_irqsave(&gr->lock, flags); gr 1170 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c if (nv04_gr_channel(gr) == chan) gr 1173 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c spin_unlock_irqrestore(&gr->lock, flags); gr 1187 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c struct nv04_gr *gr = nv04_gr(base); gr 1194 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c chan->gr = gr; gr 1200 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c spin_lock_irqsave(&gr->lock, flags); gr 1201 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c gr->chan[chan->chid] = chan; gr 1202 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c spin_unlock_irqrestore(&gr->lock, flags); gr 1211 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nv04_gr_idle(struct nvkm_gr *gr) gr 1213 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c struct nvkm_subdev *subdev = &gr->engine.subdev; gr 1274 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c struct nv04_gr *gr = nv04_gr(base); gr 1275 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 1292 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c spin_lock_irqsave(&gr->lock, flags); gr 1293 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c chan = gr->chan[chid]; gr 1306 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c nv04_gr_context_switch(gr); gr 1324 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c spin_unlock_irqrestore(&gr->lock, flags); gr 1330 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c struct nv04_gr *gr = nv04_gr(base); gr 1331 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 1418 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c struct nv04_gr *gr; gr 1420 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL))) gr 1422 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c spin_lock_init(&gr->lock); gr 1423 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c *pgr = &gr->base; gr 1425 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c return nvkm_gr_ctor(&nv04_gr, device, index, true, &gr->base); gr 401 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr; gr 414 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c #define PIPE_SAVE(gr, state, addr) \ gr 422 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c #define PIPE_RESTORE(gr, state, addr) \ gr 434 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_gr *gr = &chan->gr->base; gr 445 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv04_gr_idle(gr); gr 452 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv04_gr_idle(gr); gr 462 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv04_gr_idle(gr); gr 485 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv04_gr_idle(gr); gr 500 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv04_gr_idle(gr); gr 507 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_gr *gr = &chan->gr->base; gr 509 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv04_gr_idle(gr); gr 547 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv10_gr_channel(struct nv10_gr *gr) gr 549 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 553 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c if (chid < ARRAY_SIZE(gr->chan)) gr 554 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c chan = gr->chan[chid]; gr 562 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr = chan->gr; gr 564 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 566 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c PIPE_SAVE(gr, pipe->pipe_0x4400, 0x4400); gr 567 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c PIPE_SAVE(gr, pipe->pipe_0x0200, 0x0200); gr 568 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c PIPE_SAVE(gr, pipe->pipe_0x6400, 0x6400); gr 569 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c PIPE_SAVE(gr, pipe->pipe_0x6800, 0x6800); gr 570 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c PIPE_SAVE(gr, pipe->pipe_0x6c00, 0x6c00); gr 571 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c PIPE_SAVE(gr, pipe->pipe_0x7000, 0x7000); gr 572 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c PIPE_SAVE(gr, pipe->pipe_0x7400, 0x7400); gr 573 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c PIPE_SAVE(gr, pipe->pipe_0x7800, 0x7800); gr 574 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c PIPE_SAVE(gr, pipe->pipe_0x0040, 0x0040); gr 575 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c PIPE_SAVE(gr, pipe->pipe_0x0000, 0x0000); gr 581 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr = chan->gr; gr 583 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 587 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv04_gr_idle(&gr->base); gr 611 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c PIPE_RESTORE(gr, pipe->pipe_0x0200, 0x0200); gr 612 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv04_gr_idle(&gr->base); gr 617 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c PIPE_RESTORE(gr, pipe->pipe_0x6400, 0x6400); gr 618 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c PIPE_RESTORE(gr, pipe->pipe_0x6800, 0x6800); gr 619 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c PIPE_RESTORE(gr, pipe->pipe_0x6c00, 0x6c00); gr 620 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c PIPE_RESTORE(gr, pipe->pipe_0x7000, 0x7000); gr 621 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c PIPE_RESTORE(gr, pipe->pipe_0x7400, 0x7400); gr 622 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c PIPE_RESTORE(gr, pipe->pipe_0x7800, 0x7800); gr 623 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c PIPE_RESTORE(gr, pipe->pipe_0x4400, 0x4400); gr 624 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c PIPE_RESTORE(gr, pipe->pipe_0x0000, 0x0000); gr 625 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c PIPE_RESTORE(gr, pipe->pipe_0x0040, 0x0040); gr 626 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv04_gr_idle(&gr->base); gr 632 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr = chan->gr; gr 633 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 786 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv10_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg) gr 788 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 799 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv17_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg) gr 801 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 814 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr = chan->gr; gr 815 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 885 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr = chan->gr; gr 886 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 912 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr = chan->gr; gr 913 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 932 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv10_gr_context_switch(struct nv10_gr *gr) gr 934 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 939 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv04_gr_idle(&gr->base); gr 942 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c prev = nv10_gr_channel(gr); gr 948 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c next = gr->chan[chid]; gr 957 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr = chan->gr; gr 958 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 961 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c spin_lock_irqsave(&gr->lock, flags); gr 963 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c if (nv10_gr_channel(gr) == chan) gr 966 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c spin_unlock_irqrestore(&gr->lock, flags); gr 974 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr = chan->gr; gr 977 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c spin_lock_irqsave(&gr->lock, flags); gr 978 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c gr->chan[chan->chid] = NULL; gr 979 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c spin_unlock_irqrestore(&gr->lock, flags); gr 990 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c int offset = nv10_gr_ctx_regs_find_offset(gr, reg); \ gr 996 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c int offset = nv17_gr_ctx_regs_find_offset(gr, reg); \ gr 1005 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr = nv10_gr(base); gr 1007 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 1013 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c chan->gr = gr; gr 1038 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c spin_lock_irqsave(&gr->lock, flags); gr 1039 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c gr->chan[chan->chid] = chan; gr 1040 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c spin_unlock_irqrestore(&gr->lock, flags); gr 1051 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr = nv10_gr(base); gr 1052 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 1057 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv04_gr_idle(&gr->base); gr 1083 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr = nv10_gr(base); gr 1084 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 1100 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c spin_lock_irqsave(&gr->lock, flags); gr 1101 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c chan = gr->chan[chid]; gr 1114 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c nv10_gr_context_switch(gr); gr 1132 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c spin_unlock_irqrestore(&gr->lock, flags); gr 1138 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr = nv10_gr(base); gr 1139 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 1178 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c struct nv10_gr *gr; gr 1180 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL))) gr 1182 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c spin_lock_init(&gr->lock); gr 1183 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c *pgr = &gr->base; gr 1185 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c return nvkm_gr_ctor(func, device, index, true, &gr->base); gr 20 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c struct nv20_gr *gr = chan->gr; gr 23 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nvkm_kmap(gr->ctxtab); gr 24 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nvkm_wo32(gr->ctxtab, chan->chid * 4, inst >> 4); gr 25 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nvkm_done(gr->ctxtab); gr 33 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c struct nv20_gr *gr = chan->gr; gr 34 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 53 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nvkm_kmap(gr->ctxtab); gr 54 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nvkm_wo32(gr->ctxtab, chan->chid * 4, 0x00000000); gr 55 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nvkm_done(gr->ctxtab); gr 78 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c struct nv20_gr *gr = nv20_gr(base); gr 85 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c chan->gr = gr; gr 89 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c ret = nvkm_memory_new(gr->base.engine.subdev.device, gr 151 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c struct nv20_gr *gr = nv20_gr(base); gr 152 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 157 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nv04_gr_idle(&gr->base); gr 182 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c struct nv20_gr *gr = nv20_gr(base); gr 183 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 222 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c struct nv20_gr *gr = nv20_gr(base); gr 223 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c return nvkm_memory_new(gr->base.engine.subdev.device, gr 225 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c true, &gr->ctxtab); gr 231 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c struct nv20_gr *gr = nv20_gr(base); gr 232 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 237 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nvkm_memory_addr(gr->ctxtab) >> 4); gr 326 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c struct nv20_gr *gr = nv20_gr(base); gr 327 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c nvkm_memory_unref(&gr->ctxtab); gr 328 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c return gr; gr 335 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c struct nv20_gr *gr; gr 337 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL))) gr 339 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c *pgr = &gr->base; gr 341 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c return nvkm_gr_ctor(func, device, index, true, &gr->base); gr 27 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h struct nv20_gr *gr; gr 24 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c struct nv20_gr *gr = nv20_gr(base); gr 31 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c chan->gr = gr; gr 35 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c ret = nvkm_memory_new(gr->base.engine.subdev.device, gr 24 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c struct nv20_gr *gr = nv20_gr(base); gr 31 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c chan->gr = gr; gr 35 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c ret = nvkm_memory_new(gr->base.engine.subdev.device, gr 25 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c struct nv20_gr *gr = nv20_gr(base); gr 32 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c chan->gr = gr; gr 36 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c ret = nvkm_memory_new(gr->base.engine.subdev.device, gr 106 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c struct nv20_gr *gr = nv20_gr(base); gr 107 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 110 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c nvkm_memory_addr(gr->ctxtab) >> 4); gr 24 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c struct nv20_gr *gr = nv20_gr(base); gr 31 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c chan->gr = gr; gr 35 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c ret = nvkm_memory_new(gr->base.engine.subdev.device, gr 24 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c struct nv20_gr *gr = nv20_gr(base); gr 31 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c chan->gr = gr; gr 35 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c ret = nvkm_memory_new(gr->base.engine.subdev.device, gr 34 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nv40_gr_units(struct nvkm_gr *gr) gr 36 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c return nvkm_rd32(gr->engine.subdev.device, 0x1540); gr 78 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c struct nv40_gr *gr = chan->gr; gr 79 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c int ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size, gr 84 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nv40_grctx_fill(gr->base.engine.subdev.device, *pgpuobj); gr 95 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c struct nv40_gr *gr = chan->gr; gr 96 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 134 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c spin_lock_irqsave(&chan->gr->base.engine.lock, flags); gr 136 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c spin_unlock_irqrestore(&chan->gr->base.engine.lock, flags); gr 151 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c struct nv40_gr *gr = nv40_gr(base); gr 158 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c chan->gr = gr; gr 162 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c spin_lock_irqsave(&chan->gr->base.engine.lock, flags); gr 163 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c list_add(&chan->head, &gr->chan); gr 164 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c spin_unlock_irqrestore(&chan->gr->base.engine.lock, flags); gr 175 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c struct nv40_gr *gr = nv40_gr(base); gr 176 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 181 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c nv04_gr_idle(&gr->base); gr 234 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c struct nv40_gr *gr = nv40_gr(base); gr 236 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 251 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c spin_lock_irqsave(&gr->base.engine.lock, flags); gr 252 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c list_for_each_entry(temp, &gr->chan, head) { gr 256 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c list_add(&chan->head, &gr->chan); gr 283 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c spin_unlock_irqrestore(&gr->base.engine.lock, flags); gr 289 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c struct nv40_gr *gr = nv40_gr(base); gr 290 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 295 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c ret = nv40_grctx_init(device, &gr->size); gr 434 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c struct nv40_gr *gr; gr 436 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL))) gr 438 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c *pgr = &gr->base; gr 439 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c INIT_LIST_HEAD(&gr->chan); gr 441 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c return nvkm_gr_ctor(func, device, index, true, &gr->base); gr 24 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h struct nv40_gr *gr; gr 33 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c struct nv40_gr *gr = nv40_gr(base); gr 34 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 39 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c nv04_gr_idle(&gr->base); gr 33 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nv50_gr_units(struct nvkm_gr *gr) gr 35 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c return nvkm_rd32(gr->engine.subdev.device, 0x1540); gr 72 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c struct nv50_gr *gr = nv50_gr_chan(object)->gr; gr 73 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c int ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size, gr 77 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nv50_grctx_fill(gr->base.engine.subdev.device, *pgpuobj); gr 92 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c struct nv50_gr *gr = nv50_gr(base); gr 98 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c chan->gr = gr; gr 240 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nv50_gr_prop_trap(struct nv50_gr *gr, u32 ustatus_addr, u32 ustatus, u32 tp) gr 242 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 282 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nv50_gr_mp_trap(struct nv50_gr *gr, int tpid, int display) gr 284 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 325 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nv50_gr_tp_trap(struct nv50_gr *gr, int type, u32 ustatus_old, gr 328 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 365 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nv50_gr_mp_trap(gr, i, display); gr 379 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c gr, ustatus_addr, ustatus, i); gr 395 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, gr 398 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 587 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nv50_gr_tp_trap(gr, 6, 0x408900, 0x408600, display, gr 595 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nv50_gr_tp_trap(gr, 7, 0x408314, 0x40831c, display, gr 604 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c nv50_gr_tp_trap(gr, 8, 0x408e08, 0x408708, display, gr 622 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c struct nv50_gr *gr = nv50_gr(base); gr 623 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c struct nvkm_subdev *subdev = &gr->base.engine.subdev; gr 655 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c if (!nv50_gr_trap_handler(gr, show, chid, (u64)inst << 12, name)) gr 681 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c struct nv50_gr *gr = nv50_gr(base); gr 682 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c struct nvkm_device *device = gr->base.engine.subdev.device; gr 719 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c ret = nv50_grctx_init(device, &gr->size); gr 766 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c struct nv50_gr *gr; gr 768 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL))) gr 770 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c spin_lock_init(&gr->lock); gr 771 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c *pgr = &gr->base; gr 773 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c return nvkm_gr_ctor(func, device, index, true, &gr->base); gr 27 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h struct nv50_gr *gr; gr 53 drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c if (device->gr) gr 54 drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c nvkm_engine_tile(&device->gr->engine, region); gr 193 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c if (i == NVKM_ENGINE_GR && device->gr) { gr 194 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c int ret = nvkm_gr_tlb_flush(device->gr); gr 1322 drivers/gpu/drm/omapdrm/dss/dispc.c coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) | gr 225 drivers/gpu/drm/omapdrm/dss/omapdss.h s16 gr, gg, gb; gr 67 drivers/macintosh/windfarm_pid.c target = (s32)((integ * (s64)st->param.gr + deriv * (s64)st->param.gd + gr 118 drivers/macintosh/windfarm_pid.c integ *= st->param.gr; gr 29 drivers/macintosh/windfarm_pid.h s32 gd, gp, gr; /* PID gains */ gr 62 drivers/macintosh/windfarm_pid.h s32 gd, gp, gr; /* PID gains */ gr 167 drivers/macintosh/windfarm_pm112.c pid.gr = piddata->gr / piddata->history_len; gr 345 drivers/macintosh/windfarm_pm112.c .gr = 0, gr 395 drivers/macintosh/windfarm_pm112.c .gr = 0, gr 446 drivers/macintosh/windfarm_pm112.c .gr = 0x1277952, gr 544 drivers/macintosh/windfarm_pm121.c pid_param.gr = PM121_SYS_GR; gr 686 drivers/macintosh/windfarm_pm121.c pid_param.gr = piddata->gr / pid_param.history_len; gr 425 drivers/macintosh/windfarm_pm72.c pid.gr = mpu->pid_gr; gr 444 drivers/macintosh/windfarm_pm72.c .gr = 0, gr 456 drivers/macintosh/windfarm_pm72.c .gr = 0, gr 536 drivers/macintosh/windfarm_pm72.c .gr = 0, gr 165 drivers/macintosh/windfarm_pm81.c s32 gd, gp, gr; gr 199 drivers/macintosh/windfarm_pm81.c .gr = 0x000002fd, gr 211 drivers/macintosh/windfarm_pm81.c .gr = 0x0000072b, gr 223 drivers/macintosh/windfarm_pm81.c .gr = 0x000002fd, gr 301 drivers/macintosh/windfarm_pm81.c pid_param.gr = param->gr; gr 440 drivers/macintosh/windfarm_pm81.c pid_param.gr = piddata->gr / pid_param.history_len; gr 186 drivers/macintosh/windfarm_pm91.c pid_param.gr = piddata->gr / pid_param.history_len; gr 297 drivers/macintosh/windfarm_pm91.c .gr = 0x00000000, gr 378 drivers/macintosh/windfarm_pm91.c .gr = 0x00020000, gr 326 drivers/macintosh/windfarm_rm31.c pid.gr = mpu->pid_gr; gr 345 drivers/macintosh/windfarm_rm31.c .gr = 0, gr 358 drivers/macintosh/windfarm_rm31.c .gr = 0x06553600, gr 445 drivers/macintosh/windfarm_rm31.c .gr = 0x00100000, gr 632 drivers/media/platform/am437x/am437x-vpfe.c ((bcomp->gr & VPFE_BLK_COMP_MASK) << gr 350 drivers/media/platform/davinci/dm355_ccdc.c val = ((bcomp->gr & CCDC_BLK_COMP_MASK) << gr 361 drivers/media/platform/davinci/dm644x_ccdc.c ((bcomp->gr & CCDC_BLK_COMP_MASK) << gr 5714 drivers/media/usb/gspca/zc3xx.c u8 gr[16]; gr 5755 drivers/media/usb/gspca/zc3xx.c gr[i - 1] = (g - gp2) / 2; gr 5757 drivers/media/usb/gspca/zc3xx.c gr[0] = gp1 == 0 ? 0 : (g - gp1); gr 5761 drivers/media/usb/gspca/zc3xx.c gr[15] = (0xff - gp2) / 2; gr 5763 drivers/media/usb/gspca/zc3xx.c reg_w(gspca_dev, gr[i], 0x0130 + i); /* gradient */ gr 151 drivers/mmc/core/mmc_test.c struct mmc_test_general_result *gr; gr 538 drivers/mmc/core/mmc_test.c if (!test->gr) gr 551 drivers/mmc/core/mmc_test.c list_add_tail(&tr->link, &test->gr->tr_lst); gr 2933 drivers/mmc/core/mmc_test.c struct mmc_test_general_result *gr; gr 2952 drivers/mmc/core/mmc_test.c gr = kzalloc(sizeof(*gr), GFP_KERNEL); gr 2953 drivers/mmc/core/mmc_test.c if (gr) { gr 2954 drivers/mmc/core/mmc_test.c INIT_LIST_HEAD(&gr->tr_lst); gr 2957 drivers/mmc/core/mmc_test.c gr->card = test->card; gr 2958 drivers/mmc/core/mmc_test.c gr->testcase = i; gr 2961 drivers/mmc/core/mmc_test.c list_add_tail(&gr->link, &mmc_test_result); gr 2967 drivers/mmc/core/mmc_test.c test->gr = gr; gr 2994 drivers/mmc/core/mmc_test.c if (gr) gr 2995 drivers/mmc/core/mmc_test.c gr->result = ret; gr 3015 drivers/mmc/core/mmc_test.c struct mmc_test_general_result *gr, *grs; gr 3019 drivers/mmc/core/mmc_test.c list_for_each_entry_safe(gr, grs, &mmc_test_result, link) { gr 3022 drivers/mmc/core/mmc_test.c if (card && gr->card != card) gr 3025 drivers/mmc/core/mmc_test.c list_for_each_entry_safe(tr, trs, &gr->tr_lst, link) { gr 3030 drivers/mmc/core/mmc_test.c list_del(&gr->link); gr 3031 drivers/mmc/core/mmc_test.c kfree(gr); gr 3042 drivers/mmc/core/mmc_test.c struct mmc_test_general_result *gr; gr 3046 drivers/mmc/core/mmc_test.c list_for_each_entry(gr, &mmc_test_result, link) { gr 3049 drivers/mmc/core/mmc_test.c if (gr->card != card) gr 3052 drivers/mmc/core/mmc_test.c seq_printf(sf, "Test %d: %d\n", gr->testcase + 1, gr->result); gr 3054 drivers/mmc/core/mmc_test.c list_for_each_entry(tr, &gr->tr_lst, link) { gr 66 drivers/parisc/power.c #define MTCPU(dr, gr) MFCPU_X(dr, gr, 0, 0x12) /* move value of gr to dr[dr] */ gr 67 drivers/parisc/power.c #define MFCPU_C(dr, gr) MFCPU_X(dr, gr, 0, 0x30) /* for dr0 and dr8 only ! */ gr 68 drivers/parisc/power.c #define MFCPU_T(dr, gr) MFCPU_X(dr, 0, gr, 0xa0) /* all dr except dr0 and dr8 */ gr 1554 drivers/scsi/BusLogic.c adapter->ext_trans_enable = georeg.gr.ext_trans_enable; gr 336 drivers/scsi/BusLogic.h } gr; gr 599 drivers/staging/media/ipu3/include/intel-ipu3.h __u16 gr; gr 618 drivers/staging/media/ipu3/include/intel-ipu3.h __u8 gr; gr 665 drivers/staging/media/ipu3/include/intel-ipu3.h __u8 gr; gr 1180 drivers/staging/media/ipu3/include/intel-ipu3.h __u16 gr; gr 2275 drivers/staging/media/ipu3/include/intel-ipu3.h __u16 gr; gr 2646 drivers/staging/media/ipu3/include/intel-ipu3.h __u16 gr; gr 1399 drivers/staging/media/ipu3/ipu3-abi.h struct imgu_abi_frame_sp_plane gr; gr 69 drivers/usb/dwc2/core.c struct dwc2_gregs_backup *gr; gr 74 drivers/usb/dwc2/core.c gr = &hsotg->gr_backup; gr 76 drivers/usb/dwc2/core.c gr->gotgctl = dwc2_readl(hsotg, GOTGCTL); gr 77 drivers/usb/dwc2/core.c gr->gintmsk = dwc2_readl(hsotg, GINTMSK); gr 78 drivers/usb/dwc2/core.c gr->gahbcfg = dwc2_readl(hsotg, GAHBCFG); gr 79 drivers/usb/dwc2/core.c gr->gusbcfg = dwc2_readl(hsotg, GUSBCFG); gr 80 drivers/usb/dwc2/core.c gr->grxfsiz = dwc2_readl(hsotg, GRXFSIZ); gr 81 drivers/usb/dwc2/core.c gr->gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); gr 82 drivers/usb/dwc2/core.c gr->gdfifocfg = dwc2_readl(hsotg, GDFIFOCFG); gr 83 drivers/usb/dwc2/core.c gr->pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1); gr 84 drivers/usb/dwc2/core.c gr->glpmcfg = dwc2_readl(hsotg, GLPMCFG); gr 85 drivers/usb/dwc2/core.c gr->gi2cctl = dwc2_readl(hsotg, GI2CCTL); gr 86 drivers/usb/dwc2/core.c gr->pcgcctl = dwc2_readl(hsotg, PCGCTL); gr 88 drivers/usb/dwc2/core.c gr->valid = true; gr 101 drivers/usb/dwc2/core.c struct dwc2_gregs_backup *gr; gr 106 drivers/usb/dwc2/core.c gr = &hsotg->gr_backup; gr 107 drivers/usb/dwc2/core.c if (!gr->valid) { gr 112 drivers/usb/dwc2/core.c gr->valid = false; gr 115 drivers/usb/dwc2/core.c dwc2_writel(hsotg, gr->gotgctl, GOTGCTL); gr 116 drivers/usb/dwc2/core.c dwc2_writel(hsotg, gr->gintmsk, GINTMSK); gr 117 drivers/usb/dwc2/core.c dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG); gr 118 drivers/usb/dwc2/core.c dwc2_writel(hsotg, gr->gahbcfg, GAHBCFG); gr 119 drivers/usb/dwc2/core.c dwc2_writel(hsotg, gr->grxfsiz, GRXFSIZ); gr 120 drivers/usb/dwc2/core.c dwc2_writel(hsotg, gr->gnptxfsiz, GNPTXFSIZ); gr 121 drivers/usb/dwc2/core.c dwc2_writel(hsotg, gr->gdfifocfg, GDFIFOCFG); gr 122 drivers/usb/dwc2/core.c dwc2_writel(hsotg, gr->pcgcctl1, PCGCCTL1); gr 123 drivers/usb/dwc2/core.c dwc2_writel(hsotg, gr->glpmcfg, GLPMCFG); gr 124 drivers/usb/dwc2/core.c dwc2_writel(hsotg, gr->pcgcctl, PCGCTL); gr 125 drivers/usb/dwc2/core.c dwc2_writel(hsotg, gr->gi2cctl, GI2CCTL); gr 255 drivers/usb/dwc2/core.c struct dwc2_gregs_backup *gr; gr 259 drivers/usb/dwc2/core.c gr = &hsotg->gr_backup; gr 266 drivers/usb/dwc2/core.c pcgcctl = (gr->pcgcctl & 0xffffc000); gr 278 drivers/usb/dwc2/core.c dwc2_writel(hsotg, gr->gahbcfg | GAHBCFG_GLBL_INTR_EN, GAHBCFG); gr 287 drivers/usb/dwc2/core.c dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG); gr 5220 drivers/usb/dwc2/gadget.c struct dwc2_gregs_backup *gr; gr 5223 drivers/usb/dwc2/gadget.c gr = &hsotg->gr_backup; gr 5254 drivers/usb/dwc2/gadget.c dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG); gr 5486 drivers/usb/dwc2/hcd.c struct dwc2_gregs_backup *gr; gr 5489 drivers/usb/dwc2/hcd.c gr = &hsotg->gr_backup; gr 5516 drivers/usb/dwc2/hcd.c dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG); gr 1099 drivers/video/fbdev/omap2/omapfb/dss/dispc.c coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) | gr 366 drivers/video/fbdev/omap2/omapfb/dss/manager-sysfs.c info.cpr_coefs.gr, gr 387 drivers/video/fbdev/omap2/omapfb/dss/manager-sysfs.c &coefs.gr, &coefs.gg, &coefs.gb, gr 392 drivers/video/fbdev/omap2/omapfb/dss/manager-sysfs.c coefs.gr, coefs.gg, coefs.gb, gr 134 fs/dlm/lock.c #define modes_compat(gr, rq) \ gr 135 fs/dlm/lock.c __dlm_compat_matrix[(gr)->lkb_grmode + 1][(rq)->lkb_rqmode + 1] gr 2597 fs/dlm/lock.c static int lock_requires_bast(struct dlm_lkb *gr, int high, int cw) gr 2599 fs/dlm/lock.c if (gr->lkb_grmode == DLM_LOCK_PR && cw) { gr 2600 fs/dlm/lock.c if (gr->lkb_highbast < DLM_LOCK_EX) gr 2605 fs/dlm/lock.c if (gr->lkb_highbast < high && gr 2606 fs/dlm/lock.c !__dlm_compat_matrix[gr->lkb_grmode+1][high+1]) gr 2647 fs/dlm/lock.c static int modes_require_bast(struct dlm_lkb *gr, struct dlm_lkb *rq) gr 2649 fs/dlm/lock.c if ((gr->lkb_grmode == DLM_LOCK_PR && rq->lkb_rqmode == DLM_LOCK_CW) || gr 2650 fs/dlm/lock.c (gr->lkb_grmode == DLM_LOCK_CW && rq->lkb_rqmode == DLM_LOCK_PR)) { gr 2651 fs/dlm/lock.c if (gr->lkb_highbast < DLM_LOCK_EX) gr 2656 fs/dlm/lock.c if (gr->lkb_highbast < rq->lkb_rqmode && !modes_compat(gr, rq)) gr 2664 fs/dlm/lock.c struct dlm_lkb *gr; gr 2666 fs/dlm/lock.c list_for_each_entry(gr, head, lkb_statequeue) { gr 2668 fs/dlm/lock.c if (gr == lkb) gr 2670 fs/dlm/lock.c if (gr->lkb_bastfn && modes_require_bast(gr, lkb)) { gr 2671 fs/dlm/lock.c queue_bast(r, gr, lkb->lkb_rqmode); gr 2672 fs/dlm/lock.c gr->lkb_highbast = lkb->lkb_rqmode; gr 111 include/media/davinci/dm355_ccdc.h unsigned char gr; gr 90 include/media/davinci/dm644x_ccdc.h char gr; gr 95 include/uapi/linux/am437x-vpfe.h char gr; gr 290 include/video/omapfb_dss.h s16 gr, gg, gb; gr 88 sound/sparc/amd7930.c __u16 gr; gr 392 sound/sparc/amd7930.c sbus_writeb(((map->gr >> 0) & 0xff), amd->regs + AMD7930_DR); gr 393 sound/sparc/amd7930.c sbus_writeb(((map->gr >> 8) & 0xff), amd->regs + AMD7930_DR); gr 487 sound/sparc/amd7930.c map->gr = gx_coeff[255]; gr 490 sound/sparc/amd7930.c map->gr = gx_coeff[level]; gr 1593 tools/testing/selftests/seccomp/seccomp_bpf.c # define SYSCALL_NUM gr[20] gr 1594 tools/testing/selftests/seccomp/seccomp_bpf.c # define SYSCALL_RET gr[28]