gpu_offset 917 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset; gpu_offset 102 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c man->gpu_offset = adev->gmc.gart_start; gpu_offset 110 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c man->gpu_offset = adev->gmc.vram_start; gpu_offset 121 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c man->gpu_offset = 0; gpu_offset 269 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c addr += bo->bdev->man[mem->mem_type].gpu_offset; gpu_offset 1145 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c bo->bdev->man[bo->mem.mem_type].gpu_offset; gpu_offset 136 drivers/gpu/drm/qxl/qxl_drv.h uint64_t gpu_offset; gpu_offset 313 drivers/gpu/drm/qxl/qxl_drv.h WARN_ON_ONCE((bo->tbo.offset & slot->gpu_offset) != slot->gpu_offset); gpu_offset 316 drivers/gpu/drm/qxl/qxl_drv.h return slot->high_bits | (bo->tbo.offset - slot->gpu_offset + offset); gpu_offset 93 drivers/gpu/drm/qxl/qxl_kms.c (unsigned long)slot->gpu_offset); gpu_offset 117 drivers/gpu/drm/qxl/qxl_ttm.c slot->gpu_offset = (uint64_t)type << gpu_offset_shift; gpu_offset 119 drivers/gpu/drm/qxl/qxl_ttm.c man->gpu_offset = slot->gpu_offset; gpu_offset 1149 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 1221 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 1233 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 1245 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 1257 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 1281 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 1301 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 1505 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 1522 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 1563 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 1579 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 1591 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 1708 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 1722 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 1736 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 1819 drivers/gpu/drm/radeon/evergreen_cs.c offset = reloc->gpu_offset + gpu_offset 1865 drivers/gpu/drm/radeon/evergreen_cs.c offset = reloc->gpu_offset + gpu_offset 1900 drivers/gpu/drm/radeon/evergreen_cs.c offset = reloc->gpu_offset + gpu_offset 1928 drivers/gpu/drm/radeon/evergreen_cs.c offset = reloc->gpu_offset + gpu_offset 2025 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+1] = reloc->gpu_offset; gpu_offset 2026 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+2] = upper_32_bits(reloc->gpu_offset) & 0xff; gpu_offset 2079 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff); gpu_offset 2101 drivers/gpu/drm/radeon/evergreen_cs.c offset = reloc->gpu_offset + gpu_offset 2158 drivers/gpu/drm/radeon/evergreen_cs.c offset = reloc->gpu_offset + tmp; gpu_offset 2196 drivers/gpu/drm/radeon/evergreen_cs.c offset = reloc->gpu_offset + tmp; gpu_offset 2232 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 2248 drivers/gpu/drm/radeon/evergreen_cs.c offset = reloc->gpu_offset + gpu_offset 2270 drivers/gpu/drm/radeon/evergreen_cs.c offset = reloc->gpu_offset + gpu_offset 2292 drivers/gpu/drm/radeon/evergreen_cs.c offset = reloc->gpu_offset + gpu_offset 2378 drivers/gpu/drm/radeon/evergreen_cs.c toffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 2397 drivers/gpu/drm/radeon/evergreen_cs.c moffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 2424 drivers/gpu/drm/radeon/evergreen_cs.c offset64 = reloc->gpu_offset + offset; gpu_offset 2505 drivers/gpu/drm/radeon/evergreen_cs.c offset += reloc->gpu_offset; gpu_offset 2524 drivers/gpu/drm/radeon/evergreen_cs.c offset += reloc->gpu_offset; gpu_offset 2553 drivers/gpu/drm/radeon/evergreen_cs.c offset += reloc->gpu_offset; gpu_offset 2578 drivers/gpu/drm/radeon/evergreen_cs.c offset += reloc->gpu_offset; gpu_offset 2605 drivers/gpu/drm/radeon/evergreen_cs.c offset += reloc->gpu_offset; gpu_offset 2654 drivers/gpu/drm/radeon/evergreen_cs.c offset += reloc->gpu_offset; gpu_offset 2832 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); gpu_offset 2840 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); gpu_offset 2841 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; gpu_offset 2883 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); gpu_offset 2884 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); gpu_offset 2885 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; gpu_offset 2886 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; gpu_offset 2896 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); gpu_offset 2900 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); gpu_offset 2901 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; gpu_offset 2906 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); gpu_offset 2907 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; gpu_offset 2911 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); gpu_offset 2942 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xffffffff); gpu_offset 2943 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xffffffff); gpu_offset 2944 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; gpu_offset 2945 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; gpu_offset 2955 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+1] += (u32)(src_reloc->gpu_offset & 0xffffffff); gpu_offset 2956 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+2] += upper_32_bits(src_reloc->gpu_offset) & 0xff; gpu_offset 2957 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+4] += (u32)(dst_reloc->gpu_offset & 0xffffffff); gpu_offset 2958 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+5] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; gpu_offset 2991 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); gpu_offset 2992 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+2] += (u32)(dst2_reloc->gpu_offset & 0xfffffffc); gpu_offset 2993 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+3] += (u32)(src_reloc->gpu_offset & 0xfffffffc); gpu_offset 2994 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+4] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; gpu_offset 2995 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+5] += upper_32_bits(dst2_reloc->gpu_offset) & 0xff; gpu_offset 2996 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff; gpu_offset 3031 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); gpu_offset 3032 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); gpu_offset 3033 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); gpu_offset 3034 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; gpu_offset 3047 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); gpu_offset 3049 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); gpu_offset 3050 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; gpu_offset 3053 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); gpu_offset 3054 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; gpu_offset 3056 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); gpu_offset 3093 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); gpu_offset 3094 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); gpu_offset 3095 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); gpu_offset 3096 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; gpu_offset 3107 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); gpu_offset 3111 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); gpu_offset 3112 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; gpu_offset 3117 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); gpu_offset 3118 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; gpu_offset 3122 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); gpu_offset 3143 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); gpu_offset 3144 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+4] += (u32)(dst_reloc->gpu_offset >> 8); gpu_offset 3180 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); gpu_offset 3181 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); gpu_offset 3182 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); gpu_offset 3183 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; gpu_offset 3204 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); gpu_offset 3205 drivers/gpu/drm/radeon/evergreen_cs.c ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000; gpu_offset 1280 drivers/gpu/drm/radeon/r100.c tmp += (((u32)reloc->gpu_offset) >> 10); gpu_offset 1331 drivers/gpu/drm/radeon/r100.c ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); gpu_offset 1343 drivers/gpu/drm/radeon/r100.c ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset); gpu_offset 1357 drivers/gpu/drm/radeon/r100.c ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); gpu_offset 1598 drivers/gpu/drm/radeon/r100.c ib[idx] = idx_value + ((u32)reloc->gpu_offset); gpu_offset 1611 drivers/gpu/drm/radeon/r100.c ib[idx] = idx_value + ((u32)reloc->gpu_offset); gpu_offset 1632 drivers/gpu/drm/radeon/r100.c ib[idx] = tmp + ((u32)reloc->gpu_offset); gpu_offset 1634 drivers/gpu/drm/radeon/r100.c ib[idx] = idx_value + ((u32)reloc->gpu_offset); gpu_offset 1652 drivers/gpu/drm/radeon/r100.c ib[idx] = idx_value + ((u32)reloc->gpu_offset); gpu_offset 1670 drivers/gpu/drm/radeon/r100.c ib[idx] = idx_value + ((u32)reloc->gpu_offset); gpu_offset 1688 drivers/gpu/drm/radeon/r100.c ib[idx] = idx_value + ((u32)reloc->gpu_offset); gpu_offset 1776 drivers/gpu/drm/radeon/r100.c ib[idx] = idx_value + ((u32)reloc->gpu_offset); gpu_offset 1935 drivers/gpu/drm/radeon/r100.c ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset); gpu_offset 1949 drivers/gpu/drm/radeon/r100.c ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset); gpu_offset 191 drivers/gpu/drm/radeon/r200.c ib[idx] = idx_value + ((u32)reloc->gpu_offset); gpu_offset 204 drivers/gpu/drm/radeon/r200.c ib[idx] = idx_value + ((u32)reloc->gpu_offset); gpu_offset 228 drivers/gpu/drm/radeon/r200.c ib[idx] = tmp + ((u32)reloc->gpu_offset); gpu_offset 230 drivers/gpu/drm/radeon/r200.c ib[idx] = idx_value + ((u32)reloc->gpu_offset); gpu_offset 274 drivers/gpu/drm/radeon/r200.c ib[idx] = idx_value + ((u32)reloc->gpu_offset); gpu_offset 368 drivers/gpu/drm/radeon/r200.c ib[idx] = idx_value + ((u32)reloc->gpu_offset); gpu_offset 679 drivers/gpu/drm/radeon/r300.c ib[idx] = idx_value + ((u32)reloc->gpu_offset); gpu_offset 692 drivers/gpu/drm/radeon/r300.c ib[idx] = idx_value + ((u32)reloc->gpu_offset); gpu_offset 721 drivers/gpu/drm/radeon/r300.c ((idx_value & ~31) + (u32)reloc->gpu_offset); gpu_offset 730 drivers/gpu/drm/radeon/r300.c tmp = idx_value + ((u32)reloc->gpu_offset); gpu_offset 1091 drivers/gpu/drm/radeon/r300.c ib[idx] = idx_value + ((u32)reloc->gpu_offset); gpu_offset 1136 drivers/gpu/drm/radeon/r300.c ib[idx] = idx_value + ((u32)reloc->gpu_offset); gpu_offset 1201 drivers/gpu/drm/radeon/r300.c ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); gpu_offset 1023 drivers/gpu/drm/radeon/r600_cs.c ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 1085 drivers/gpu/drm/radeon/r600_cs.c ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 1087 drivers/gpu/drm/radeon/r600_cs.c track->vgt_strmout_bo_mc[tmp] = reloc->gpu_offset; gpu_offset 1106 drivers/gpu/drm/radeon/r600_cs.c ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 1215 drivers/gpu/drm/radeon/r600_cs.c ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 1246 drivers/gpu/drm/radeon/r600_cs.c ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 1282 drivers/gpu/drm/radeon/r600_cs.c ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 1285 drivers/gpu/drm/radeon/r600_cs.c track->cb_color_bo_mc[tmp] = reloc->gpu_offset; gpu_offset 1296 drivers/gpu/drm/radeon/r600_cs.c ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 1298 drivers/gpu/drm/radeon/r600_cs.c track->db_bo_mc = reloc->gpu_offset; gpu_offset 1309 drivers/gpu/drm/radeon/r600_cs.c ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 1378 drivers/gpu/drm/radeon/r600_cs.c ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 1387 drivers/gpu/drm/radeon/r600_cs.c ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 1673 drivers/gpu/drm/radeon/r600_cs.c offset = reloc->gpu_offset + gpu_offset 1714 drivers/gpu/drm/radeon/r600_cs.c offset = reloc->gpu_offset + gpu_offset 1766 drivers/gpu/drm/radeon/r600_cs.c offset = reloc->gpu_offset + gpu_offset 1806 drivers/gpu/drm/radeon/r600_cs.c offset = reloc->gpu_offset + tmp; gpu_offset 1836 drivers/gpu/drm/radeon/r600_cs.c offset = reloc->gpu_offset + tmp; gpu_offset 1862 drivers/gpu/drm/radeon/r600_cs.c ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 1878 drivers/gpu/drm/radeon/r600_cs.c offset = reloc->gpu_offset + gpu_offset 1900 drivers/gpu/drm/radeon/r600_cs.c offset = reloc->gpu_offset + gpu_offset 1965 drivers/gpu/drm/radeon/r600_cs.c base_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 1979 drivers/gpu/drm/radeon/r600_cs.c mip_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 2009 drivers/gpu/drm/radeon/r600_cs.c offset64 = reloc->gpu_offset + offset; gpu_offset 2119 drivers/gpu/drm/radeon/r600_cs.c ib[idx+1] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); gpu_offset 2152 drivers/gpu/drm/radeon/r600_cs.c offset += reloc->gpu_offset; gpu_offset 2171 drivers/gpu/drm/radeon/r600_cs.c offset += reloc->gpu_offset; gpu_offset 2200 drivers/gpu/drm/radeon/r600_cs.c offset += reloc->gpu_offset; gpu_offset 2225 drivers/gpu/drm/radeon/r600_cs.c offset += reloc->gpu_offset; gpu_offset 2249 drivers/gpu/drm/radeon/r600_cs.c offset += reloc->gpu_offset; gpu_offset 2411 drivers/gpu/drm/radeon/r600_cs.c ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); gpu_offset 2417 drivers/gpu/drm/radeon/r600_cs.c ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); gpu_offset 2418 drivers/gpu/drm/radeon/r600_cs.c ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; gpu_offset 2445 drivers/gpu/drm/radeon/r600_cs.c ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); gpu_offset 2449 drivers/gpu/drm/radeon/r600_cs.c ib[idx+5] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); gpu_offset 2450 drivers/gpu/drm/radeon/r600_cs.c ib[idx+6] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; gpu_offset 2455 drivers/gpu/drm/radeon/r600_cs.c ib[idx+5] += (u32)(src_reloc->gpu_offset & 0xfffffffc); gpu_offset 2456 drivers/gpu/drm/radeon/r600_cs.c ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff; gpu_offset 2460 drivers/gpu/drm/radeon/r600_cs.c ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); gpu_offset 2470 drivers/gpu/drm/radeon/r600_cs.c ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); gpu_offset 2471 drivers/gpu/drm/radeon/r600_cs.c ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); gpu_offset 2472 drivers/gpu/drm/radeon/r600_cs.c ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; gpu_offset 2473 drivers/gpu/drm/radeon/r600_cs.c ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; gpu_offset 2481 drivers/gpu/drm/radeon/r600_cs.c ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); gpu_offset 2482 drivers/gpu/drm/radeon/r600_cs.c ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); gpu_offset 2483 drivers/gpu/drm/radeon/r600_cs.c ib[idx+3] += upper_32_bits(src_reloc->gpu_offset) & 0xff; gpu_offset 2484 drivers/gpu/drm/radeon/r600_cs.c ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) & 0xff) << 16; gpu_offset 2516 drivers/gpu/drm/radeon/r600_cs.c ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); gpu_offset 2517 drivers/gpu/drm/radeon/r600_cs.c ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000; gpu_offset 463 drivers/gpu/drm/radeon/radeon.h uint64_t gpu_offset; gpu_offset 877 drivers/gpu/drm/radeon/radeon_cs.c (*cs_reloc)->gpu_offset = gpu_offset 879 drivers/gpu/drm/radeon/radeon_cs.c (*cs_reloc)->gpu_offset |= relocs_chunk->kdata[idx + 0]; gpu_offset 593 drivers/gpu/drm/radeon/radeon_object.c lobj->gpu_offset = radeon_bo_gpu_offset(bo); gpu_offset 598 drivers/gpu/drm/radeon/radeon_object.c lobj->gpu_offset = radeon_bo_gpu_offset(lobj->robj); gpu_offset 90 drivers/gpu/drm/radeon/radeon_ttm.c man->gpu_offset = rdev->mc.gtt_start; gpu_offset 112 drivers/gpu/drm/radeon/radeon_ttm.c man->gpu_offset = rdev->mc.vram_start; gpu_offset 592 drivers/gpu/drm/radeon/radeon_uvd.c start = reloc->gpu_offset; gpu_offset 489 drivers/gpu/drm/radeon/radeon_vce.c start = reloc->gpu_offset; gpu_offset 87 drivers/gpu/drm/ttm/ttm_bo.c drm_printf(p, " gpu_offset: 0x%08llX\n", man->gpu_offset); gpu_offset 404 drivers/gpu/drm/ttm/ttm_bo.c bdev->man[bo->mem.mem_type].gpu_offset; gpu_offset 758 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c man->gpu_offset = 0; gpu_offset 771 drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c man->gpu_offset = 0; gpu_offset 180 include/drm/ttm/ttm_bo_driver.h uint64_t gpu_offset; /* GPU address space is independent of CPU word size */