gpu                32 arch/powerpc/platforms/ps3/system-bus.c 	int gpu;
gpu               114 arch/powerpc/platforms/ps3/system-bus.c 	usage_hack.gpu++;
gpu               115 arch/powerpc/platforms/ps3/system-bus.c 	if (usage_hack.gpu > 1) {
gpu               139 arch/powerpc/platforms/ps3/system-bus.c 	usage_hack.gpu--;
gpu               140 arch/powerpc/platforms/ps3/system-bus.c 	if (usage_hack.gpu) {
gpu               401 arch/x86/events/intel/rapl.c RAPL_EVENT_ATTR_STR(energy-gpu  ,   rapl_gpu, "event=0x04");
gpu               407 arch/x86/events/intel/rapl.c RAPL_EVENT_ATTR_STR(energy-gpu.unit  ,   rapl_gpu_unit, "Joules");
gpu               416 arch/x86/events/intel/rapl.c RAPL_EVENT_ATTR_STR(energy-gpu.scale,     rapl_gpu_scale, "2.3283064365386962890625e-10");
gpu               496 drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/amd/amdgpu
gpu              1297 drivers/gpu/drm/amd/amdkfd/kfd_crat.c 			if (!peer_dev->gpu)
gpu              1299 drivers/gpu/drm/amd/amdkfd/kfd_crat.c 			if (peer_dev->gpu->hive_id != kdev->hive_id)
gpu              1305 drivers/gpu/drm/amd/amdkfd/kfd_crat.c 				&avail_size, kdev, peer_dev->gpu,
gpu               844 drivers/gpu/drm/amd/amdkfd/kfd_priv.h int kfd_topology_add_device(struct kfd_dev *gpu);
gpu               845 drivers/gpu/drm/amd/amdkfd/kfd_priv.h int kfd_topology_remove_device(struct kfd_dev *gpu);
gpu                94 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	return top_dev->gpu;
gpu               105 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 		if (top_dev->gpu && top_dev->gpu->pdev == pdev) {
gpu               106 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 			device = top_dev->gpu;
gpu               123 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 		if (top_dev->gpu && top_dev->gpu->kgd == kgd) {
gpu               124 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 			device = top_dev->gpu;
gpu               478 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	if (dev->gpu) {
gpu               480 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 			__ilog2_u32(dev->gpu->device_info->num_of_watch_points);
gpu               492 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 		if (dev->gpu->device_info->asic_family == CHIP_TONGA)
gpu               503 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 				dev->gpu->mec_fw_version);
gpu               507 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 				dev->gpu->sdma_fw_version);
gpu               923 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	if (!kdev->gpu) {
gpu              1062 drivers/gpu/drm/amd/amdkfd/kfd_topology.c static uint32_t kfd_generate_gpu_id(struct kfd_dev *gpu)
gpu              1070 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	if (!gpu)
gpu              1073 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	amdgpu_amdkfd_get_local_mem_info(gpu->kgd, &local_mem_info);
gpu              1078 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	buf[0] = gpu->pdev->devfn;
gpu              1079 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	buf[1] = gpu->pdev->subsystem_vendor |
gpu              1080 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 		(gpu->pdev->subsystem_device << 16);
gpu              1081 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	buf[2] = pci_domain_nr(gpu->pdev->bus);
gpu              1082 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	buf[3] = gpu->pdev->device;
gpu              1083 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	buf[4] = gpu->pdev->bus->number;
gpu              1097 drivers/gpu/drm/amd/amdkfd/kfd_topology.c static struct kfd_topology_device *kfd_assign_gpu(struct kfd_dev *gpu)
gpu              1107 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 		if (!gpu->device_info->needs_iommu_device &&
gpu              1111 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 		if (!dev->gpu && (dev->node_props.simd_count > 0)) {
gpu              1112 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 			dev->gpu = gpu;
gpu              1146 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	amdgpu_amdkfd_get_local_mem_info(dev->gpu->kgd, &local_mem_info);
gpu              1160 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	if (!dev || !dev->gpu)
gpu              1163 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	pcie_capability_read_dword(dev->gpu->pdev,
gpu              1171 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	if (!dev->gpu->pci_atomic_requested ||
gpu              1172 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	    dev->gpu->device_info->asic_family == CHIP_HAWAII)
gpu              1190 drivers/gpu/drm/amd/amdkfd/kfd_topology.c int kfd_topology_add_device(struct kfd_dev *gpu)
gpu              1204 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	gpu_id = kfd_generate_gpu_id(gpu);
gpu              1216 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	dev = kfd_assign_gpu(gpu);
gpu              1219 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 						    COMPUTE_UNIT_GPU, gpu,
gpu              1250 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 		dev = kfd_assign_gpu(gpu);
gpu              1258 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	gpu->id = gpu_id;
gpu              1268 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	amdgpu_amdkfd_get_cu_info(dev->gpu->kgd, &cu_info);
gpu              1270 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	strncpy(dev->node_props.name, gpu->device_info->asic_name,
gpu              1276 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	dev->node_props.vendor_id = gpu->pdev->vendor;
gpu              1277 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	dev->node_props.device_id = gpu->pdev->device;
gpu              1278 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	dev->node_props.location_id = pci_dev_id(gpu->pdev);
gpu              1280 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 		amdgpu_amdkfd_get_max_engine_clock_in_mhz(dev->gpu->kgd);
gpu              1284 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 		gpu->shared_resources.drm_render_minor;
gpu              1286 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	dev->node_props.hive_id = gpu->hive_id;
gpu              1287 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	dev->node_props.num_sdma_engines = gpu->device_info->num_sdma_engines;
gpu              1289 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 				gpu->device_info->num_xgmi_sdma_engines;
gpu              1291 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 		dev->gpu->dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) ?
gpu              1292 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 		amdgpu_amdkfd_get_num_gws(dev->gpu->kgd) : 0;
gpu              1297 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	switch (dev->gpu->device_info->asic_family) {
gpu              1328 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 		     dev->gpu->device_info->asic_family);
gpu              1335 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	if (dev->gpu->device_info->needs_iommu_device)
gpu              1345 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	if (dev->gpu->device_info->asic_family == CHIP_CARRIZO) {
gpu              1351 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 	ctx = amdgpu_ras_get_context((struct amdgpu_device *)(dev->gpu->kgd));
gpu              1374 drivers/gpu/drm/amd/amdkfd/kfd_topology.c int kfd_topology_remove_device(struct kfd_dev *gpu)
gpu              1383 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 		if (dev->gpu == gpu) {
gpu              1419 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 			*kdev = top_dev->gpu;
gpu              1473 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 		if (!dev->gpu) {
gpu              1478 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 		seq_printf(m, "Node %u, gpu_id %x:\n", i++, dev->gpu->id);
gpu              1479 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 		r = dqm_debugfs_hqds(m, dev->gpu->dqm);
gpu              1498 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 		if (!dev->gpu) {
gpu              1503 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 		seq_printf(m, "Node %u, gpu_id %x:\n", i++, dev->gpu->id);
gpu              1504 drivers/gpu/drm/amd/amdkfd/kfd_topology.c 		r = pm_debugfs_runlist(m, &dev->gpu->dqm->packets);
gpu               166 drivers/gpu/drm/amd/amdkfd/kfd_topology.h 	struct kfd_dev			*gpu;
gpu                89 drivers/gpu/drm/armada/armada_trace.h #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/armada
gpu                67 drivers/gpu/drm/drm_trace.h #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm
gpu                88 drivers/gpu/drm/etnaviv/etnaviv_buffer.c static void etnaviv_cmd_select_pipe(struct etnaviv_gpu *gpu,
gpu                93 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 	lockdep_assert_held(&gpu->lock);
gpu               101 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 	if (gpu->exec_state == ETNA_PIPE_2D)
gpu               103 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 	else if (gpu->exec_state == ETNA_PIPE_3D)
gpu               114 drivers/gpu/drm/etnaviv/etnaviv_buffer.c static void etnaviv_buffer_dump(struct etnaviv_gpu *gpu,
gpu               120 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 	dev_info(gpu->dev, "virt %p phys 0x%08x free 0x%08x\n",
gpu               122 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 			&gpu->mmu_context->cmdbuf_mapping) +
gpu               150 drivers/gpu/drm/etnaviv/etnaviv_buffer.c static u32 etnaviv_buffer_reserve(struct etnaviv_gpu *gpu,
gpu               157 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 				     &gpu->mmu_context->cmdbuf_mapping) +
gpu               161 drivers/gpu/drm/etnaviv/etnaviv_buffer.c u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu)
gpu               163 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
gpu               165 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 	lockdep_assert_held(&gpu->lock);
gpu               172 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 		 etnaviv_cmdbuf_get_va(buffer, &gpu->mmu_context->cmdbuf_mapping)
gpu               178 drivers/gpu/drm/etnaviv/etnaviv_buffer.c u16 etnaviv_buffer_config_mmuv2(struct etnaviv_gpu *gpu, u32 mtlb_addr, u32 safe_addr)
gpu               180 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
gpu               182 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 	lockdep_assert_held(&gpu->lock);
gpu               186 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 	if (gpu->identity.features & chipFeatures_PIPE_3D) {
gpu               196 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 	if (gpu->identity.features & chipFeatures_PIPE_2D) {
gpu               213 drivers/gpu/drm/etnaviv/etnaviv_buffer.c u16 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu, unsigned short id)
gpu               215 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
gpu               217 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 	lockdep_assert_held(&gpu->lock);
gpu               231 drivers/gpu/drm/etnaviv/etnaviv_buffer.c void etnaviv_buffer_end(struct etnaviv_gpu *gpu)
gpu               233 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
gpu               237 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 	lockdep_assert_held(&gpu->lock);
gpu               239 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 	if (gpu->exec_state == ETNA_PIPE_2D)
gpu               241 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 	else if (gpu->exec_state == ETNA_PIPE_3D)
gpu               251 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 		link_target = etnaviv_buffer_reserve(gpu, buffer, dwords);
gpu               256 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 		if (gpu->exec_state == ETNA_PIPE_3D)
gpu               275 drivers/gpu/drm/etnaviv/etnaviv_buffer.c void etnaviv_sync_point_queue(struct etnaviv_gpu *gpu, unsigned int event)
gpu               277 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
gpu               281 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 	lockdep_assert_held(&gpu->lock);
gpu               288 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 	target = etnaviv_buffer_reserve(gpu, buffer, dwords);
gpu               300 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 		 etnaviv_cmdbuf_get_va(buffer, &gpu->mmu_context->cmdbuf_mapping)
gpu               314 drivers/gpu/drm/etnaviv/etnaviv_buffer.c void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state,
gpu               318 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 	struct etnaviv_cmdbuf *buffer = &gpu->buffer;
gpu               322 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 	bool switch_context = gpu->exec_state != exec_state;
gpu               323 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 	bool switch_mmu_context = gpu->mmu_context != mmu_context;
gpu               324 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 	unsigned int new_flush_seq = READ_ONCE(gpu->mmu_context->flush_seq);
gpu               325 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 	bool need_flush = switch_mmu_context || gpu->flush_seq != new_flush_seq;
gpu               327 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 	lockdep_assert_held(&gpu->lock);
gpu               330 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 		etnaviv_buffer_dump(gpu, buffer, 0, 0x50);
gpu               333 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 					    &gpu->mmu_context->cmdbuf_mapping);
gpu               349 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 			if (gpu->mmu_context->global->version == ETNAVIV_IOMMU_V1)
gpu               360 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 		if (switch_mmu_context && gpu->sec_mode == ETNA_SEC_KERNEL)
gpu               363 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 		target = etnaviv_buffer_reserve(gpu, buffer, extra_dwords);
gpu               371 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 			struct etnaviv_iommu_context *old_context = gpu->mmu_context;
gpu               374 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 			gpu->mmu_context = mmu_context;
gpu               380 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 			if (gpu->mmu_context->global->version == ETNAVIV_IOMMU_V1) {
gpu               392 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 				    gpu->sec_mode == ETNA_SEC_KERNEL) {
gpu               394 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 						etnaviv_iommuv2_get_pta_id(gpu->mmu_context);
gpu               400 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 				if (gpu->sec_mode == ETNA_SEC_NONE)
gpu               401 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 					flush |= etnaviv_iommuv2_get_mtlb_addr(gpu->mmu_context);
gpu               411 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 			gpu->flush_seq = new_flush_seq;
gpu               415 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 			etnaviv_cmd_select_pipe(gpu, buffer, exec_state);
gpu               416 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 			gpu->exec_state = exec_state;
gpu               421 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 					&gpu->mmu_context->cmdbuf_mapping);
gpu               436 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 	return_target = etnaviv_buffer_reserve(gpu, buffer, return_dwords);
gpu               443 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 	if (gpu->exec_state == ETNA_PIPE_2D) {
gpu               459 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 		 etnaviv_cmdbuf_get_va(buffer, &gpu->mmu_context->cmdbuf_mapping)
gpu               465 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 			etnaviv_cmdbuf_get_va(cmdbuf, &gpu->mmu_context->cmdbuf_mapping),
gpu               488 drivers/gpu/drm/etnaviv/etnaviv_buffer.c 		etnaviv_buffer_dump(gpu, buffer, 0, 0x50);
gpu                16 drivers/gpu/drm/etnaviv/etnaviv_cmd_parser.c 	struct etnaviv_gpu *gpu;
gpu                93 drivers/gpu/drm/etnaviv/etnaviv_cmd_parser.c 		dev_warn_once(state->gpu->dev,
gpu               123 drivers/gpu/drm/etnaviv/etnaviv_cmd_parser.c 		dev_warn_ratelimited(state->gpu->dev,
gpu               147 drivers/gpu/drm/etnaviv/etnaviv_cmd_parser.c bool etnaviv_cmd_validate_one(struct etnaviv_gpu *gpu, u32 *stream,
gpu               156 drivers/gpu/drm/etnaviv/etnaviv_cmd_parser.c 	state.gpu = gpu;
gpu               189 drivers/gpu/drm/etnaviv/etnaviv_cmd_parser.c 				dev_err(gpu->dev, "%s: op %u not permitted at offset %tu\n",
gpu               200 drivers/gpu/drm/etnaviv/etnaviv_cmd_parser.c 		dev_err(gpu->dev, "%s: commands overflow end of buffer: %tu > %u\n",
gpu                37 drivers/gpu/drm/etnaviv/etnaviv_drv.c 		struct etnaviv_gpu *g = priv->gpu[i];
gpu                44 drivers/gpu/drm/etnaviv/etnaviv_drv.c 				priv->gpu[i] = NULL;
gpu                67 drivers/gpu/drm/etnaviv/etnaviv_drv.c 		struct etnaviv_gpu *gpu = priv->gpu[i];
gpu                70 drivers/gpu/drm/etnaviv/etnaviv_drv.c 		if (gpu) {
gpu                71 drivers/gpu/drm/etnaviv/etnaviv_drv.c 			rq = &gpu->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
gpu                93 drivers/gpu/drm/etnaviv/etnaviv_drv.c 		struct etnaviv_gpu *gpu = priv->gpu[i];
gpu                95 drivers/gpu/drm/etnaviv/etnaviv_drv.c 		if (gpu)
gpu               129 drivers/gpu/drm/etnaviv/etnaviv_drv.c static int etnaviv_mmu_show(struct etnaviv_gpu *gpu, struct seq_file *m)
gpu               134 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	seq_printf(m, "Active Objects (%s):\n", dev_name(gpu->dev));
gpu               141 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	mutex_lock(&gpu->lock);
gpu               142 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	mmu_context = gpu->mmu_context;
gpu               145 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	mutex_unlock(&gpu->lock);
gpu               159 drivers/gpu/drm/etnaviv/etnaviv_drv.c static void etnaviv_buffer_dump(struct etnaviv_gpu *gpu, struct seq_file *m)
gpu               161 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	struct etnaviv_cmdbuf *buf = &gpu->buffer;
gpu               180 drivers/gpu/drm/etnaviv/etnaviv_drv.c static int etnaviv_ring_show(struct etnaviv_gpu *gpu, struct seq_file *m)
gpu               182 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	seq_printf(m, "Ring Buffer (%s): ", dev_name(gpu->dev));
gpu               184 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	mutex_lock(&gpu->lock);
gpu               185 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	etnaviv_buffer_dump(gpu, m);
gpu               186 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	mutex_unlock(&gpu->lock);
gpu               206 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	struct etnaviv_gpu *gpu;
gpu               207 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	int (*show)(struct etnaviv_gpu *gpu, struct seq_file *m) =
gpu               213 drivers/gpu/drm/etnaviv/etnaviv_drv.c 		gpu = priv->gpu[i];
gpu               214 drivers/gpu/drm/etnaviv/etnaviv_drv.c 		if (!gpu)
gpu               217 drivers/gpu/drm/etnaviv/etnaviv_drv.c 		ret = show(gpu, m);
gpu               260 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	struct etnaviv_gpu *gpu;
gpu               265 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	gpu = priv->gpu[args->pipe];
gpu               266 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	if (!gpu)
gpu               269 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	return etnaviv_gpu_get_param(gpu, args->param, &args->value);
gpu               358 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	struct etnaviv_gpu *gpu;
gpu               366 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	gpu = priv->gpu[args->pipe];
gpu               367 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	if (!gpu)
gpu               373 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	return etnaviv_gpu_wait_fence_interruptible(gpu, args->fence,
gpu               408 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	struct etnaviv_gpu *gpu;
gpu               417 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	gpu = priv->gpu[args->pipe];
gpu               418 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	if (!gpu)
gpu               428 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	ret = etnaviv_gem_wait_bo(gpu, obj, timeout);
gpu               440 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	struct etnaviv_gpu *gpu;
gpu               445 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	gpu = priv->gpu[args->pipe];
gpu               446 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	if (!gpu)
gpu               449 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	return etnaviv_pm_query_dom(gpu, args);
gpu               457 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	struct etnaviv_gpu *gpu;
gpu               462 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	gpu = priv->gpu[args->pipe];
gpu               463 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	if (!gpu)
gpu               466 drivers/gpu/drm/etnaviv/etnaviv_drv.c 	return etnaviv_pm_query_sig(gpu, args);
gpu                37 drivers/gpu/drm/etnaviv/etnaviv_drv.h 	struct etnaviv_gpu *gpu[ETNA_MAX_PIPES];
gpu                71 drivers/gpu/drm/etnaviv/etnaviv_drv.h u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu);
gpu                72 drivers/gpu/drm/etnaviv/etnaviv_drv.h u16 etnaviv_buffer_config_mmuv2(struct etnaviv_gpu *gpu, u32 mtlb_addr, u32 safe_addr);
gpu                73 drivers/gpu/drm/etnaviv/etnaviv_drv.h u16 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu, unsigned short id);
gpu                74 drivers/gpu/drm/etnaviv/etnaviv_drv.h void etnaviv_buffer_end(struct etnaviv_gpu *gpu);
gpu                75 drivers/gpu/drm/etnaviv/etnaviv_drv.h void etnaviv_sync_point_queue(struct etnaviv_gpu *gpu, unsigned int event);
gpu                76 drivers/gpu/drm/etnaviv/etnaviv_drv.h void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state,
gpu                80 drivers/gpu/drm/etnaviv/etnaviv_drv.h bool etnaviv_cmd_validate_one(struct etnaviv_gpu *gpu,
gpu                82 drivers/gpu/drm/etnaviv/etnaviv_dump.c 	struct etnaviv_gpu *gpu)
gpu                89 drivers/gpu/drm/etnaviv/etnaviv_dump.c 		reg->value = gpu_read(gpu, etnaviv_dump_registers[i]);
gpu               115 drivers/gpu/drm/etnaviv/etnaviv_dump.c 	struct etnaviv_gpu *gpu = submit->gpu;
gpu               128 drivers/gpu/drm/etnaviv/etnaviv_dump.c 	mutex_lock(&gpu->mmu_context->lock);
gpu               130 drivers/gpu/drm/etnaviv/etnaviv_dump.c 	mmu_size = etnaviv_iommu_dump_size(gpu->mmu_context);
gpu               137 drivers/gpu/drm/etnaviv/etnaviv_dump.c 		    mmu_size + gpu->buffer.size + submit->cmdbuf.size;
gpu               160 drivers/gpu/drm/etnaviv/etnaviv_dump.c 		mutex_unlock(&gpu->mmu_context->lock);
gpu               161 drivers/gpu/drm/etnaviv/etnaviv_dump.c 		dev_warn(gpu->dev, "failed to allocate devcoredump file\n");
gpu               171 drivers/gpu/drm/etnaviv/etnaviv_dump.c 	etnaviv_core_dump_registers(&iter, gpu);
gpu               172 drivers/gpu/drm/etnaviv/etnaviv_dump.c 	etnaviv_core_dump_mmu(&iter, gpu->mmu_context, mmu_size);
gpu               173 drivers/gpu/drm/etnaviv/etnaviv_dump.c 	etnaviv_core_dump_mem(&iter, ETDUMP_BUF_RING, gpu->buffer.vaddr,
gpu               174 drivers/gpu/drm/etnaviv/etnaviv_dump.c 			      gpu->buffer.size,
gpu               175 drivers/gpu/drm/etnaviv/etnaviv_dump.c 			      etnaviv_cmdbuf_get_va(&gpu->buffer,
gpu               176 drivers/gpu/drm/etnaviv/etnaviv_dump.c 					&gpu->mmu_context->cmdbuf_mapping));
gpu               181 drivers/gpu/drm/etnaviv/etnaviv_dump.c 					&gpu->mmu_context->cmdbuf_mapping));
gpu               183 drivers/gpu/drm/etnaviv/etnaviv_dump.c 	mutex_unlock(&gpu->mmu_context->lock);
gpu               228 drivers/gpu/drm/etnaviv/etnaviv_dump.c 	dev_coredumpv(gpu->dev, iter.start, iter.data - iter.start, GFP_KERNEL);
gpu               433 drivers/gpu/drm/etnaviv/etnaviv_gem.c int etnaviv_gem_wait_bo(struct etnaviv_gpu *gpu, struct drm_gem_object *obj,
gpu               438 drivers/gpu/drm/etnaviv/etnaviv_gem.c 	return etnaviv_gpu_wait_obj_inactive(gpu, etnaviv_obj, timeout);
gpu                42 drivers/gpu/drm/etnaviv/etnaviv_gem.h 	struct etnaviv_gpu *gpu;     /* non-null if active */
gpu                96 drivers/gpu/drm/etnaviv/etnaviv_gem.h 	struct etnaviv_gpu *gpu;
gpu               114 drivers/gpu/drm/etnaviv/etnaviv_gem.h int etnaviv_gem_wait_bo(struct etnaviv_gpu *gpu, struct drm_gem_object *obj,
gpu                32 drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c 		struct etnaviv_gpu *gpu, size_t nr_bos, size_t nr_pmrs)
gpu                49 drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c 	submit->gpu = gpu;
gpu               379 drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c 		pm_runtime_put_autosuspend(submit->gpu->dev);
gpu               406 drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c 	wake_up_all(&submit->gpu->fence_event);
gpu               412 drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c 		mutex_lock(&submit->gpu->fence_lock);
gpu               413 drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c 		idr_remove(&submit->gpu->fence_idr, submit->out_fence_id);
gpu               414 drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c 		mutex_unlock(&submit->gpu->fence_lock);
gpu               436 drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c 	struct etnaviv_gpu *gpu;
gpu               446 drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c 	gpu = priv->gpu[args->pipe];
gpu               447 drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c 	if (!gpu)
gpu               525 drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c 	submit = submit_create(dev, gpu, args->nr_bos, args->nr_pmrs);
gpu               547 drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c 	    !etnaviv_cmd_validate_one(gpu, stream, args->stream_size / 4,
gpu                43 drivers/gpu/drm/etnaviv/etnaviv_gpu.c int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
gpu                45 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	struct etnaviv_drm_private *priv = gpu->drm->dev_private;
gpu                49 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		*value = gpu->identity.model;
gpu                53 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		*value = gpu->identity.revision;
gpu                57 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		*value = gpu->identity.features;
gpu                61 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		*value = gpu->identity.minor_features0;
gpu                65 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		*value = gpu->identity.minor_features1;
gpu                69 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		*value = gpu->identity.minor_features2;
gpu                73 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		*value = gpu->identity.minor_features3;
gpu                77 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		*value = gpu->identity.minor_features4;
gpu                81 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		*value = gpu->identity.minor_features5;
gpu                85 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		*value = gpu->identity.minor_features6;
gpu                89 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		*value = gpu->identity.minor_features7;
gpu                93 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		*value = gpu->identity.minor_features8;
gpu                97 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		*value = gpu->identity.minor_features9;
gpu               101 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		*value = gpu->identity.minor_features10;
gpu               105 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		*value = gpu->identity.minor_features11;
gpu               109 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		*value = gpu->identity.stream_count;
gpu               113 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		*value = gpu->identity.register_max;
gpu               117 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		*value = gpu->identity.thread_count;
gpu               121 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		*value = gpu->identity.vertex_cache_size;
gpu               125 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		*value = gpu->identity.shader_core_count;
gpu               129 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		*value = gpu->identity.pixel_pipes;
gpu               133 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		*value = gpu->identity.vertex_output_buffer_size;
gpu               137 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		*value = gpu->identity.buffer_size;
gpu               141 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		*value = gpu->identity.instruction_count;
gpu               145 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		*value = gpu->identity.num_constants;
gpu               149 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		*value = gpu->identity.varyings_count;
gpu               160 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
gpu               168 drivers/gpu/drm/etnaviv/etnaviv_gpu.c #define etnaviv_is_model_rev(gpu, mod, rev) \
gpu               169 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	((gpu)->identity.model == chipModel_##mod && \
gpu               170 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	 (gpu)->identity.revision == rev)
gpu               174 drivers/gpu/drm/etnaviv/etnaviv_gpu.c static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
gpu               176 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->identity.minor_features0 &
gpu               181 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
gpu               182 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
gpu               183 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
gpu               184 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
gpu               186 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.stream_count = etnaviv_field(specs[0],
gpu               188 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.register_max = etnaviv_field(specs[0],
gpu               190 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.thread_count = etnaviv_field(specs[0],
gpu               192 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
gpu               194 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.shader_core_count = etnaviv_field(specs[0],
gpu               196 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.pixel_pipes = etnaviv_field(specs[0],
gpu               198 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.vertex_output_buffer_size =
gpu               202 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.buffer_size = etnaviv_field(specs[1],
gpu               204 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.instruction_count = etnaviv_field(specs[1],
gpu               206 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.num_constants = etnaviv_field(specs[1],
gpu               209 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.varyings_count = etnaviv_field(specs[2],
gpu               216 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu->identity.stream_count = streams;
gpu               220 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->identity.stream_count == 0) {
gpu               221 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		if (gpu->identity.model >= 0x1000)
gpu               222 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu->identity.stream_count = 4;
gpu               224 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu->identity.stream_count = 1;
gpu               228 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->identity.register_max)
gpu               229 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.register_max = 1 << gpu->identity.register_max;
gpu               230 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	else if (gpu->identity.model == chipModel_GC400)
gpu               231 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.register_max = 32;
gpu               233 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.register_max = 64;
gpu               236 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->identity.thread_count)
gpu               237 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.thread_count = 1 << gpu->identity.thread_count;
gpu               238 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	else if (gpu->identity.model == chipModel_GC400)
gpu               239 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.thread_count = 64;
gpu               240 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	else if (gpu->identity.model == chipModel_GC500 ||
gpu               241 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		 gpu->identity.model == chipModel_GC530)
gpu               242 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.thread_count = 128;
gpu               244 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.thread_count = 256;
gpu               246 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->identity.vertex_cache_size == 0)
gpu               247 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.vertex_cache_size = 8;
gpu               249 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->identity.shader_core_count == 0) {
gpu               250 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		if (gpu->identity.model >= 0x1000)
gpu               251 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu->identity.shader_core_count = 2;
gpu               253 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu->identity.shader_core_count = 1;
gpu               256 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->identity.pixel_pipes == 0)
gpu               257 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.pixel_pipes = 1;
gpu               260 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->identity.vertex_output_buffer_size) {
gpu               261 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.vertex_output_buffer_size =
gpu               262 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			1 << gpu->identity.vertex_output_buffer_size;
gpu               263 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	} else if (gpu->identity.model == chipModel_GC400) {
gpu               264 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		if (gpu->identity.revision < 0x4000)
gpu               265 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu->identity.vertex_output_buffer_size = 512;
gpu               266 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		else if (gpu->identity.revision < 0x4200)
gpu               267 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu->identity.vertex_output_buffer_size = 256;
gpu               269 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu->identity.vertex_output_buffer_size = 128;
gpu               271 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.vertex_output_buffer_size = 512;
gpu               274 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	switch (gpu->identity.instruction_count) {
gpu               276 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
gpu               277 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		    gpu->identity.model == chipModel_GC880)
gpu               278 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu->identity.instruction_count = 512;
gpu               280 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu->identity.instruction_count = 256;
gpu               284 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.instruction_count = 1024;
gpu               288 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.instruction_count = 2048;
gpu               292 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.instruction_count = 256;
gpu               296 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->identity.num_constants == 0)
gpu               297 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.num_constants = 168;
gpu               299 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->identity.varyings_count == 0) {
gpu               300 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
gpu               301 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu->identity.varyings_count = 12;
gpu               303 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu->identity.varyings_count = 8;
gpu               310 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
gpu               311 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	    etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
gpu               312 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	    etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
gpu               313 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	    etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
gpu               314 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	    etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
gpu               315 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	    etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
gpu               316 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	    etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
gpu               317 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	    etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
gpu               318 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	    etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
gpu               319 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	    etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
gpu               320 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	    etnaviv_is_model_rev(gpu, GC880, 0x5106))
gpu               321 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.varyings_count -= 1;
gpu               324 drivers/gpu/drm/etnaviv/etnaviv_gpu.c static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
gpu               328 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
gpu               332 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.model    = chipModel_GC500;
gpu               333 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.revision = etnaviv_field(chipIdentity,
gpu               337 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
gpu               338 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
gpu               346 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		if ((gpu->identity.model & 0xff00) == 0x0400 &&
gpu               347 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		    gpu->identity.model != chipModel_GC420) {
gpu               348 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu->identity.model = gpu->identity.model & 0x0400;
gpu               352 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
gpu               353 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
gpu               354 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
gpu               361 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 				gpu->identity.revision = 0x1051;
gpu               372 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) {
gpu               373 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu->identity.model = chipModel_GC3000;
gpu               374 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu->identity.revision &= 0xffff;
gpu               378 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	dev_info(gpu->dev, "model: GC%x, revision: %x\n",
gpu               379 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		 gpu->identity.model, gpu->identity.revision);
gpu               381 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
gpu               386 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (etnaviv_fill_identity_from_hwdb(gpu))
gpu               389 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
gpu               392 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->identity.model == chipModel_GC700)
gpu               393 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
gpu               395 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if ((gpu->identity.model == chipModel_GC500 &&
gpu               396 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	     gpu->identity.revision < 2) ||
gpu               397 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	    (gpu->identity.model == chipModel_GC300 &&
gpu               398 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	     gpu->identity.revision < 0x2000)) {
gpu               404 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.minor_features0 = 0;
gpu               405 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.minor_features1 = 0;
gpu               406 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.minor_features2 = 0;
gpu               407 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.minor_features3 = 0;
gpu               408 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.minor_features4 = 0;
gpu               409 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.minor_features5 = 0;
gpu               411 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.minor_features0 =
gpu               412 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
gpu               414 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->identity.minor_features0 &
gpu               416 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.minor_features1 =
gpu               417 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
gpu               418 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.minor_features2 =
gpu               419 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
gpu               420 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.minor_features3 =
gpu               421 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
gpu               422 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.minor_features4 =
gpu               423 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
gpu               424 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.minor_features5 =
gpu               425 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
gpu               429 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->identity.model == chipModel_GC600)
gpu               430 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
gpu               439 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	etnaviv_hw_specs(gpu);
gpu               442 drivers/gpu/drm/etnaviv/etnaviv_gpu.c static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
gpu               444 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
gpu               446 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
gpu               449 drivers/gpu/drm/etnaviv/etnaviv_gpu.c static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu)
gpu               451 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->identity.minor_features2 &
gpu               453 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		clk_set_rate(gpu->clk_core,
gpu               454 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			     gpu->base_rate_core >> gpu->freq_scale);
gpu               455 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		clk_set_rate(gpu->clk_shader,
gpu               456 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			     gpu->base_rate_shader >> gpu->freq_scale);
gpu               458 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		unsigned int fscale = 1 << (6 - gpu->freq_scale);
gpu               459 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
gpu               463 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		etnaviv_gpu_load_clock(gpu, clock);
gpu               467 drivers/gpu/drm/etnaviv/etnaviv_gpu.c static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
gpu               478 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		unsigned int fscale = 1 << (6 - gpu->freq_scale);
gpu               480 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		etnaviv_gpu_load_clock(gpu, control);
gpu               484 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
gpu               486 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		if (gpu->sec_mode == ETNA_SEC_KERNEL) {
gpu               487 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL,
gpu               492 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
gpu               500 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
gpu               504 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
gpu               507 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
gpu               511 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			dev_dbg(gpu->dev, "FE is not idle\n");
gpu               516 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
gpu               521 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			dev_dbg(gpu->dev, "GPU is not idle\n");
gpu               527 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
gpu               534 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
gpu               535 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
gpu               537 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
gpu               546 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	etnaviv_gpu_update_clock(gpu);
gpu               551 drivers/gpu/drm/etnaviv/etnaviv_gpu.c static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
gpu               556 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
gpu               560 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->identity.revision == 0x4301 ||
gpu               561 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	    gpu->identity.revision == 0x4302)
gpu               564 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc);
gpu               566 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS);
gpu               569 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->identity.model >= chipModel_GC400 &&
gpu               570 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	    gpu->identity.model != chipModel_GC420 &&
gpu               571 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	    !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12))
gpu               578 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->identity.revision < 0x5000 &&
gpu               579 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	    gpu->identity.minor_features0 & chipMinorFeatures0_HZ &&
gpu               580 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	    !(gpu->identity.minor_features1 &
gpu               584 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->identity.revision < 0x5422)
gpu               588 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
gpu               589 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	    etnaviv_is_model_rev(gpu, GC2000, 0x5108))
gpu               595 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
gpu               598 drivers/gpu/drm/etnaviv/etnaviv_gpu.c void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
gpu               600 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address);
gpu               601 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
gpu               605 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->sec_mode == ETNA_SEC_KERNEL) {
gpu               606 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL,
gpu               612 drivers/gpu/drm/etnaviv/etnaviv_gpu.c static void etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu)
gpu               614 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	u32 address = etnaviv_cmdbuf_get_va(&gpu->buffer,
gpu               615 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 				&gpu->mmu_context->cmdbuf_mapping);
gpu               619 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	etnaviv_iommu_restore(gpu, gpu->mmu_context);
gpu               622 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	prefetch = etnaviv_buffer_init(gpu);
gpu               624 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	etnaviv_gpu_start_fe(gpu, address, prefetch);
gpu               627 drivers/gpu/drm/etnaviv/etnaviv_gpu.c static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
gpu               635 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
gpu               636 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	    etnaviv_is_model_rev(gpu, GC4000, 0x5222)) {
gpu               641 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) ||
gpu               642 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	    etnaviv_is_model_rev(gpu, GC1000, 0x5040)) {
gpu               647 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if ((gpu->identity.revision > 0x5420) &&
gpu               648 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	    (gpu->identity.features & chipFeatures_PIPE_3D))
gpu               651 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER);
gpu               655 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
gpu               658 drivers/gpu/drm/etnaviv/etnaviv_gpu.c static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
gpu               660 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
gpu               661 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	     etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
gpu               662 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	    gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
gpu               665 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
gpu               667 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		if (gpu->identity.revision == 0x5007)
gpu               672 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
gpu               676 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	etnaviv_gpu_enable_mlcg(gpu);
gpu               682 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu_write(gpu, VIVS_HI_AXI_CONFIG,
gpu               687 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
gpu               688 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
gpu               693 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
gpu               696 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->sec_mode == ETNA_SEC_KERNEL) {
gpu               697 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);
gpu               699 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val);
gpu               703 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	etnaviv_gpu_setup_pulse_eater(gpu);
gpu               705 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
gpu               708 drivers/gpu/drm/etnaviv/etnaviv_gpu.c int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
gpu               710 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	struct etnaviv_drm_private *priv = gpu->drm->dev_private;
gpu               713 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	ret = pm_runtime_get_sync(gpu->dev);
gpu               715 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		dev_err(gpu->dev, "Failed to enable GPU power domain\n");
gpu               719 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	etnaviv_hw_identify(gpu);
gpu               721 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->identity.model == 0) {
gpu               722 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		dev_err(gpu->dev, "Unknown GPU model\n");
gpu               728 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->identity.features & chipFeatures_PIPE_VG &&
gpu               729 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	    gpu->identity.features & chipFeatures_FE20) {
gpu               730 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
gpu               739 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) &&
gpu               740 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	    (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB))
gpu               741 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->sec_mode = ETNA_SEC_KERNEL;
gpu               743 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	ret = etnaviv_hw_reset(gpu);
gpu               745 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		dev_err(gpu->dev, "GPU reset failed\n");
gpu               749 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	ret = etnaviv_iommu_global_init(gpu);
gpu               762 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
gpu               763 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	    (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
gpu               764 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		u32 dma_mask = (u32)dma_get_required_mask(gpu->dev);
gpu               770 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		dev_info(gpu->dev, "Need to move linear window on MC1.0, disabling TS\n");
gpu               772 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
gpu               776 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer,
gpu               779 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		dev_err(gpu->dev, "could not create command buffer\n");
gpu               784 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	spin_lock_init(&gpu->event_spinlock);
gpu               785 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	init_completion(&gpu->event_free);
gpu               786 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
gpu               787 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	for (i = 0; i < ARRAY_SIZE(gpu->event); i++)
gpu               788 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		complete(&gpu->event_free);
gpu               791 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	mutex_lock(&gpu->lock);
gpu               792 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	etnaviv_gpu_hw_init(gpu);
gpu               793 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu->exec_state = -1;
gpu               794 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	mutex_unlock(&gpu->lock);
gpu               796 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	pm_runtime_mark_last_busy(gpu->dev);
gpu               797 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	pm_runtime_put_autosuspend(gpu->dev);
gpu               799 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu->initialized = true;
gpu               804 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	pm_runtime_mark_last_busy(gpu->dev);
gpu               805 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	pm_runtime_put_autosuspend(gpu->dev);
gpu               816 drivers/gpu/drm/etnaviv/etnaviv_gpu.c static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
gpu               820 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
gpu               821 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	debug->state[0]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
gpu               824 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
gpu               825 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		debug->state[1]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
gpu               835 drivers/gpu/drm/etnaviv/etnaviv_gpu.c int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
gpu               841 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
gpu               843 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	ret = pm_runtime_get_sync(gpu->dev);
gpu               847 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
gpu               848 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
gpu               849 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
gpu               850 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
gpu               852 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	verify_dma(gpu, &debug);
gpu               856 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		   gpu->identity.features);
gpu               858 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		   gpu->identity.minor_features0);
gpu               860 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		   gpu->identity.minor_features1);
gpu               862 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		   gpu->identity.minor_features2);
gpu               864 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		   gpu->identity.minor_features3);
gpu               866 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		   gpu->identity.minor_features4);
gpu               868 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		   gpu->identity.minor_features5);
gpu               870 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		   gpu->identity.minor_features6);
gpu               872 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		   gpu->identity.minor_features7);
gpu               874 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		   gpu->identity.minor_features8);
gpu               876 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		   gpu->identity.minor_features9);
gpu               878 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		   gpu->identity.minor_features10);
gpu               880 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		   gpu->identity.minor_features11);
gpu               884 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu->identity.stream_count);
gpu               886 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu->identity.register_max);
gpu               888 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu->identity.thread_count);
gpu               890 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu->identity.vertex_cache_size);
gpu               892 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu->identity.shader_core_count);
gpu               894 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu->identity.pixel_pipes);
gpu               896 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu->identity.vertex_output_buffer_size);
gpu               898 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu->identity.buffer_size);
gpu               900 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu->identity.instruction_count);
gpu               902 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu->identity.num_constants);
gpu               904 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu->identity.varyings_count);
gpu               908 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
gpu               936 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
gpu               937 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
gpu               938 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
gpu               939 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
gpu               967 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	pm_runtime_mark_last_busy(gpu->dev);
gpu               968 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	pm_runtime_put_autosuspend(gpu->dev);
gpu               974 drivers/gpu/drm/etnaviv/etnaviv_gpu.c void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu)
gpu               978 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	dev_err(gpu->dev, "recover hung GPU!\n");
gpu               980 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (pm_runtime_get_sync(gpu->dev) < 0)
gpu               983 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	mutex_lock(&gpu->lock);
gpu               985 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	etnaviv_hw_reset(gpu);
gpu               988 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	spin_lock(&gpu->event_spinlock);
gpu               989 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	for_each_set_bit_from(i, gpu->event_bitmap, ETNA_NR_EVENTS)
gpu               990 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		complete(&gpu->event_free);
gpu               991 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
gpu               992 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	spin_unlock(&gpu->event_spinlock);
gpu               994 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	etnaviv_gpu_hw_init(gpu);
gpu               995 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu->exec_state = -1;
gpu               996 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu->mmu_context = NULL;
gpu               998 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	mutex_unlock(&gpu->lock);
gpu               999 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	pm_runtime_mark_last_busy(gpu->dev);
gpu              1000 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	pm_runtime_put_autosuspend(gpu->dev);
gpu              1005 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	struct etnaviv_gpu *gpu;
gpu              1023 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	return dev_name(f->gpu->dev);
gpu              1030 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0;
gpu              1047 drivers/gpu/drm/etnaviv/etnaviv_gpu.c static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
gpu              1055 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	lockdep_assert_held(&gpu->lock);
gpu              1061 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	f->gpu = gpu;
gpu              1063 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
gpu              1064 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		       gpu->fence_context, ++gpu->next_fence);
gpu              1079 drivers/gpu/drm/etnaviv/etnaviv_gpu.c static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
gpu              1088 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		ret = wait_for_completion_timeout(&gpu->event_free, timeout);
gpu              1091 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			dev_err(gpu->dev, "wait_for_completion_timeout failed");
gpu              1099 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	spin_lock(&gpu->event_spinlock);
gpu              1102 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS);
gpu              1105 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		memset(&gpu->event[event], 0, sizeof(struct etnaviv_event));
gpu              1106 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		set_bit(event, gpu->event_bitmap);
gpu              1109 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	spin_unlock(&gpu->event_spinlock);
gpu              1115 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		complete(&gpu->event_free);
gpu              1120 drivers/gpu/drm/etnaviv/etnaviv_gpu.c static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
gpu              1122 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (!test_bit(event, gpu->event_bitmap)) {
gpu              1123 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		dev_warn(gpu->dev, "event %u is already marked as free",
gpu              1126 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		clear_bit(event, gpu->event_bitmap);
gpu              1127 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		complete(&gpu->event_free);
gpu              1134 drivers/gpu/drm/etnaviv/etnaviv_gpu.c int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
gpu              1146 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	fence = idr_find(&gpu->fence_idr, id);
gpu              1181 drivers/gpu/drm/etnaviv/etnaviv_gpu.c int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
gpu              1192 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	ret = wait_event_interruptible_timeout(gpu->fence_event,
gpu              1203 drivers/gpu/drm/etnaviv/etnaviv_gpu.c static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu,
gpu              1213 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			etnaviv_perfmon_process(gpu, pmr, submit->exec_state);
gpu              1217 drivers/gpu/drm/etnaviv/etnaviv_gpu.c static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
gpu              1223 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
gpu              1225 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
gpu              1228 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
gpu              1230 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
gpu              1232 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
gpu              1235 drivers/gpu/drm/etnaviv/etnaviv_gpu.c static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
gpu              1242 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
gpu              1251 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
gpu              1253 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
gpu              1256 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
gpu              1258 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
gpu              1265 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	struct etnaviv_gpu *gpu = submit->gpu;
gpu              1271 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		ret = pm_runtime_get_sync(gpu->dev);
gpu              1287 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	ret = event_alloc(gpu, nr_events, event);
gpu              1293 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	mutex_lock(&gpu->lock);
gpu              1295 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu_fence = etnaviv_gpu_fence_alloc(gpu);
gpu              1298 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			event_free(gpu, event[i]);
gpu              1303 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (!gpu->mmu_context) {
gpu              1305 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->mmu_context = submit->mmu_context;
gpu              1306 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		etnaviv_gpu_start_fe_idleloop(gpu);
gpu              1308 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		etnaviv_iommu_context_get(gpu->mmu_context);
gpu              1309 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		submit->prev_mmu_context = gpu->mmu_context;
gpu              1313 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
gpu              1315 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->event[event[1]].submit = submit;
gpu              1316 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		etnaviv_sync_point_queue(gpu, event[1]);
gpu              1319 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu->event[event[0]].fence = gpu_fence;
gpu              1321 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	etnaviv_buffer_queue(gpu, submit->exec_state, submit->mmu_context,
gpu              1325 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post;
gpu              1327 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->event[event[2]].submit = submit;
gpu              1328 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		etnaviv_sync_point_queue(gpu, event[2]);
gpu              1332 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	mutex_unlock(&gpu->lock);
gpu              1339 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
gpu              1341 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	struct etnaviv_event *event = &gpu->event[gpu->sync_point_event];
gpu              1342 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
gpu              1344 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	event->sync_point(gpu, event);
gpu              1346 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	event_free(gpu, gpu->sync_point_event);
gpu              1349 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	etnaviv_gpu_start_fe(gpu, addr + 2, 2);
gpu              1352 drivers/gpu/drm/etnaviv/etnaviv_gpu.c static void dump_mmu_fault(struct etnaviv_gpu *gpu)
gpu              1357 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->sec_mode == ETNA_SEC_NONE)
gpu              1362 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	status = gpu_read(gpu, status_reg);
gpu              1363 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status);
gpu              1371 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		if (gpu->sec_mode == ETNA_SEC_NONE)
gpu              1376 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		dev_err_ratelimited(gpu->dev, "MMU %d fault addr 0x%08x\n", i,
gpu              1377 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 				    gpu_read(gpu, address_reg));
gpu              1383 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	struct etnaviv_gpu *gpu = data;
gpu              1386 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
gpu              1391 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		pm_runtime_mark_last_busy(gpu->dev);
gpu              1393 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
gpu              1396 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			dev_err(gpu->dev, "AXI bus error\n");
gpu              1401 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			dump_mmu_fault(gpu);
gpu              1412 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			dev_dbg(gpu->dev, "event %u\n", event);
gpu              1414 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			if (gpu->event[event].sync_point) {
gpu              1415 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 				gpu->sync_point_event = event;
gpu              1416 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 				queue_work(gpu->wq, &gpu->sync_point_work);
gpu              1419 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			fence = gpu->event[event].fence;
gpu              1423 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			gpu->event[event].fence = NULL;
gpu              1434 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			if (fence_after(fence->seqno, gpu->completed_fence))
gpu              1435 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 				gpu->completed_fence = fence->seqno;
gpu              1438 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			event_free(gpu, event);
gpu              1447 drivers/gpu/drm/etnaviv/etnaviv_gpu.c static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
gpu              1451 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->clk_reg) {
gpu              1452 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		ret = clk_prepare_enable(gpu->clk_reg);
gpu              1457 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->clk_bus) {
gpu              1458 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		ret = clk_prepare_enable(gpu->clk_bus);
gpu              1463 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->clk_core) {
gpu              1464 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		ret = clk_prepare_enable(gpu->clk_core);
gpu              1469 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->clk_shader) {
gpu              1470 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		ret = clk_prepare_enable(gpu->clk_shader);
gpu              1478 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->clk_core)
gpu              1479 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		clk_disable_unprepare(gpu->clk_core);
gpu              1481 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->clk_bus)
gpu              1482 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		clk_disable_unprepare(gpu->clk_bus);
gpu              1487 drivers/gpu/drm/etnaviv/etnaviv_gpu.c static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
gpu              1489 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->clk_shader)
gpu              1490 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		clk_disable_unprepare(gpu->clk_shader);
gpu              1491 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->clk_core)
gpu              1492 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		clk_disable_unprepare(gpu->clk_core);
gpu              1493 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->clk_bus)
gpu              1494 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		clk_disable_unprepare(gpu->clk_bus);
gpu              1495 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->clk_reg)
gpu              1496 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		clk_disable_unprepare(gpu->clk_reg);
gpu              1501 drivers/gpu/drm/etnaviv/etnaviv_gpu.c int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms)
gpu              1506 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
gpu              1508 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		if ((idle & gpu->idle_mask) == gpu->idle_mask)
gpu              1512 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			dev_warn(gpu->dev,
gpu              1522 drivers/gpu/drm/etnaviv/etnaviv_gpu.c static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
gpu              1524 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->initialized && gpu->mmu_context) {
gpu              1526 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		mutex_lock(&gpu->lock);
gpu              1527 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		etnaviv_buffer_end(gpu);
gpu              1528 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		mutex_unlock(&gpu->lock);
gpu              1535 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		etnaviv_gpu_wait_idle(gpu, 100);
gpu              1537 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		etnaviv_iommu_context_put(gpu->mmu_context);
gpu              1538 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->mmu_context = NULL;
gpu              1541 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu->exec_state = -1;
gpu              1543 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	return etnaviv_gpu_clk_disable(gpu);
gpu              1547 drivers/gpu/drm/etnaviv/etnaviv_gpu.c static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
gpu              1551 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	ret = mutex_lock_killable(&gpu->lock);
gpu              1555 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	etnaviv_gpu_update_clock(gpu);
gpu              1556 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	etnaviv_gpu_hw_init(gpu);
gpu              1558 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	mutex_unlock(&gpu->lock);
gpu              1577 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	struct etnaviv_gpu *gpu = cdev->devdata;
gpu              1579 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	*state = gpu->freq_scale;
gpu              1588 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	struct etnaviv_gpu *gpu = cdev->devdata;
gpu              1590 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	mutex_lock(&gpu->lock);
gpu              1591 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu->freq_scale = state;
gpu              1592 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (!pm_runtime_suspended(gpu->dev))
gpu              1593 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		etnaviv_gpu_update_clock(gpu);
gpu              1594 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	mutex_unlock(&gpu->lock);
gpu              1610 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
gpu              1614 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->cooling = thermal_of_cooling_device_register(dev->of_node,
gpu              1615 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 				(char *)dev_name(dev), gpu, &cooling_ops);
gpu              1616 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		if (IS_ERR(gpu->cooling))
gpu              1617 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			return PTR_ERR(gpu->cooling);
gpu              1620 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0);
gpu              1621 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (!gpu->wq) {
gpu              1626 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	ret = etnaviv_sched_init(gpu);
gpu              1631 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	ret = pm_runtime_get_sync(gpu->dev);
gpu              1633 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	ret = etnaviv_gpu_clk_enable(gpu);
gpu              1639 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu->drm = drm;
gpu              1640 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu->fence_context = dma_fence_context_alloc(1);
gpu              1641 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	idr_init(&gpu->fence_idr);
gpu              1642 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	spin_lock_init(&gpu->fence_spinlock);
gpu              1644 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	INIT_WORK(&gpu->sync_point_work, sync_point_worker);
gpu              1645 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	init_waitqueue_head(&gpu->fence_event);
gpu              1647 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	priv->gpu[priv->num_gpus++] = gpu;
gpu              1649 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	pm_runtime_mark_last_busy(gpu->dev);
gpu              1650 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	pm_runtime_put_autosuspend(gpu->dev);
gpu              1655 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	etnaviv_sched_fini(gpu);
gpu              1658 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	destroy_workqueue(gpu->wq);
gpu              1662 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		thermal_cooling_device_unregister(gpu->cooling);
gpu              1670 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
gpu              1672 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	DBG("%s", dev_name(gpu->dev));
gpu              1674 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	flush_workqueue(gpu->wq);
gpu              1675 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	destroy_workqueue(gpu->wq);
gpu              1677 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	etnaviv_sched_fini(gpu);
gpu              1680 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	pm_runtime_get_sync(gpu->dev);
gpu              1681 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	pm_runtime_put_sync_suspend(gpu->dev);
gpu              1683 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	etnaviv_gpu_hw_suspend(gpu);
gpu              1686 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->initialized) {
gpu              1687 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		etnaviv_cmdbuf_free(&gpu->buffer);
gpu              1688 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		etnaviv_iommu_global_fini(gpu);
gpu              1689 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->initialized = false;
gpu              1692 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu->drm = NULL;
gpu              1693 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	idr_destroy(&gpu->fence_idr);
gpu              1696 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		thermal_cooling_device_unregister(gpu->cooling);
gpu              1697 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu->cooling = NULL;
gpu              1716 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	struct etnaviv_gpu *gpu;
gpu              1719 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
gpu              1720 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (!gpu)
gpu              1723 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu->dev = &pdev->dev;
gpu              1724 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	mutex_init(&gpu->lock);
gpu              1725 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	mutex_init(&gpu->fence_lock);
gpu              1728 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu->mmio = devm_platform_ioremap_resource(pdev, 0);
gpu              1729 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (IS_ERR(gpu->mmio))
gpu              1730 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		return PTR_ERR(gpu->mmio);
gpu              1733 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu->irq = platform_get_irq(pdev, 0);
gpu              1734 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->irq < 0) {
gpu              1735 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		dev_err(dev, "failed to get irq: %d\n", gpu->irq);
gpu              1736 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		return gpu->irq;
gpu              1739 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
gpu              1740 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			       dev_name(gpu->dev), gpu);
gpu              1742 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
gpu              1747 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu->clk_reg = devm_clk_get(&pdev->dev, "reg");
gpu              1748 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	DBG("clk_reg: %p", gpu->clk_reg);
gpu              1749 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (IS_ERR(gpu->clk_reg))
gpu              1750 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->clk_reg = NULL;
gpu              1752 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu->clk_bus = devm_clk_get(&pdev->dev, "bus");
gpu              1753 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	DBG("clk_bus: %p", gpu->clk_bus);
gpu              1754 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (IS_ERR(gpu->clk_bus))
gpu              1755 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->clk_bus = NULL;
gpu              1757 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu->clk_core = devm_clk_get(&pdev->dev, "core");
gpu              1758 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	DBG("clk_core: %p", gpu->clk_core);
gpu              1759 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (IS_ERR(gpu->clk_core))
gpu              1760 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->clk_core = NULL;
gpu              1761 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu->base_rate_core = clk_get_rate(gpu->clk_core);
gpu              1763 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu->clk_shader = devm_clk_get(&pdev->dev, "shader");
gpu              1764 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	DBG("clk_shader: %p", gpu->clk_shader);
gpu              1765 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (IS_ERR(gpu->clk_shader))
gpu              1766 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		gpu->clk_shader = NULL;
gpu              1767 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
gpu              1770 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	dev_set_drvdata(dev, gpu);
gpu              1777 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	pm_runtime_use_autosuspend(gpu->dev);
gpu              1778 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	pm_runtime_set_autosuspend_delay(gpu->dev, 200);
gpu              1779 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	pm_runtime_enable(gpu->dev);
gpu              1800 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
gpu              1804 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (atomic_read(&gpu->sched.hw_rq_count))
gpu              1808 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE;
gpu              1809 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
gpu              1813 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	return etnaviv_gpu_hw_suspend(gpu);
gpu              1818 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
gpu              1821 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	ret = etnaviv_gpu_clk_enable(gpu);
gpu              1826 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 	if (gpu->drm && gpu->initialized) {
gpu              1827 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 		ret = etnaviv_gpu_hw_resume(gpu);
gpu              1829 drivers/gpu/drm/etnaviv/etnaviv_gpu.c 			etnaviv_gpu_clk_disable(gpu);
gpu                85 drivers/gpu/drm/etnaviv/etnaviv_gpu.h 	void (*sync_point)(struct etnaviv_gpu *gpu, struct etnaviv_event *event);
gpu               150 drivers/gpu/drm/etnaviv/etnaviv_gpu.h static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data)
gpu               152 drivers/gpu/drm/etnaviv/etnaviv_gpu.h 	writel(data, gpu->mmio + reg);
gpu               155 drivers/gpu/drm/etnaviv/etnaviv_gpu.h static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg)
gpu               157 drivers/gpu/drm/etnaviv/etnaviv_gpu.h 	return readl(gpu->mmio + reg);
gpu               160 drivers/gpu/drm/etnaviv/etnaviv_gpu.h int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value);
gpu               162 drivers/gpu/drm/etnaviv/etnaviv_gpu.h int etnaviv_gpu_init(struct etnaviv_gpu *gpu);
gpu               163 drivers/gpu/drm/etnaviv/etnaviv_gpu.h bool etnaviv_fill_identity_from_hwdb(struct etnaviv_gpu *gpu);
gpu               166 drivers/gpu/drm/etnaviv/etnaviv_gpu.h int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m);
gpu               169 drivers/gpu/drm/etnaviv/etnaviv_gpu.h void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu);
gpu               170 drivers/gpu/drm/etnaviv/etnaviv_gpu.h void etnaviv_gpu_retire(struct etnaviv_gpu *gpu);
gpu               171 drivers/gpu/drm/etnaviv/etnaviv_gpu.h int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
gpu               173 drivers/gpu/drm/etnaviv/etnaviv_gpu.h int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
gpu               176 drivers/gpu/drm/etnaviv/etnaviv_gpu.h int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu);
gpu               177 drivers/gpu/drm/etnaviv/etnaviv_gpu.h void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu);
gpu               178 drivers/gpu/drm/etnaviv/etnaviv_gpu.h int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms);
gpu               179 drivers/gpu/drm/etnaviv/etnaviv_gpu.h void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch);
gpu                39 drivers/gpu/drm/etnaviv/etnaviv_hwdb.c bool etnaviv_fill_identity_from_hwdb(struct etnaviv_gpu *gpu)
gpu                41 drivers/gpu/drm/etnaviv/etnaviv_hwdb.c 	struct etnaviv_chip_identity *ident = &gpu->identity;
gpu                89 drivers/gpu/drm/etnaviv/etnaviv_iommu.c static void etnaviv_iommuv1_restore(struct etnaviv_gpu *gpu,
gpu                96 drivers/gpu/drm/etnaviv/etnaviv_iommu.c 	gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, context->global->memory_base);
gpu                97 drivers/gpu/drm/etnaviv/etnaviv_iommu.c 	gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, context->global->memory_base);
gpu                98 drivers/gpu/drm/etnaviv/etnaviv_iommu.c 	gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, context->global->memory_base);
gpu                99 drivers/gpu/drm/etnaviv/etnaviv_iommu.c 	gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, context->global->memory_base);
gpu               100 drivers/gpu/drm/etnaviv/etnaviv_iommu.c 	gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, context->global->memory_base);
gpu               105 drivers/gpu/drm/etnaviv/etnaviv_iommu.c 	gpu_write(gpu, VIVS_MC_MMU_FE_PAGE_TABLE, pgtable);
gpu               106 drivers/gpu/drm/etnaviv/etnaviv_iommu.c 	gpu_write(gpu, VIVS_MC_MMU_TX_PAGE_TABLE, pgtable);
gpu               107 drivers/gpu/drm/etnaviv/etnaviv_iommu.c 	gpu_write(gpu, VIVS_MC_MMU_PE_PAGE_TABLE, pgtable);
gpu               108 drivers/gpu/drm/etnaviv/etnaviv_iommu.c 	gpu_write(gpu, VIVS_MC_MMU_PEZ_PAGE_TABLE, pgtable);
gpu               109 drivers/gpu/drm/etnaviv/etnaviv_iommu.c 	gpu_write(gpu, VIVS_MC_MMU_RA_PAGE_TABLE, pgtable);
gpu               165 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c static void etnaviv_iommuv2_restore_nonsec(struct etnaviv_gpu *gpu,
gpu               172 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c 	if (gpu_read(gpu, VIVS_MMUv2_CONTROL) & VIVS_MMUv2_CONTROL_ENABLE)
gpu               175 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c 	prefetch = etnaviv_buffer_config_mmuv2(gpu,
gpu               178 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c 	etnaviv_gpu_start_fe(gpu, (u32)etnaviv_cmdbuf_get_pa(&gpu->buffer),
gpu               180 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c 	etnaviv_gpu_wait_idle(gpu, 100);
gpu               182 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c 	gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE);
gpu               185 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c static void etnaviv_iommuv2_restore_sec(struct etnaviv_gpu *gpu,
gpu               192 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c 	if (gpu_read(gpu, VIVS_MMUv2_SEC_CONTROL) & VIVS_MMUv2_SEC_CONTROL_ENABLE)
gpu               195 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c 	gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_LOW,
gpu               197 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c 	gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_HIGH,
gpu               199 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c 	gpu_write(gpu, VIVS_MMUv2_PTA_CONTROL, VIVS_MMUv2_PTA_CONTROL_ENABLE);
gpu               201 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c 	gpu_write(gpu, VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW,
gpu               203 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c 	gpu_write(gpu, VIVS_MMUv2_SEC_SAFE_ADDR_LOW,
gpu               205 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c 	gpu_write(gpu, VIVS_MMUv2_SAFE_ADDRESS_CONFIG,
gpu               215 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c 	prefetch = etnaviv_buffer_config_pta(gpu, v2_context->id);
gpu               216 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c 	etnaviv_gpu_start_fe(gpu, (u32)etnaviv_cmdbuf_get_pa(&gpu->buffer),
gpu               218 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c 	etnaviv_gpu_wait_idle(gpu, 100);
gpu               220 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c 	gpu_write(gpu, VIVS_MMUv2_SEC_CONTROL, VIVS_MMUv2_SEC_CONTROL_ENABLE);
gpu               236 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c static void etnaviv_iommuv2_restore(struct etnaviv_gpu *gpu,
gpu               239 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c 	switch (gpu->sec_mode) {
gpu               241 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c 		etnaviv_iommuv2_restore_nonsec(gpu, context);
gpu               244 drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c 		etnaviv_iommuv2_restore_sec(gpu, context);
gpu               350 drivers/gpu/drm/etnaviv/etnaviv_mmu.c void etnaviv_iommu_restore(struct etnaviv_gpu *gpu,
gpu               353 drivers/gpu/drm/etnaviv/etnaviv_mmu.c 	context->global->ops->restore(gpu, context);
gpu               435 drivers/gpu/drm/etnaviv/etnaviv_mmu.c int etnaviv_iommu_global_init(struct etnaviv_gpu *gpu)
gpu               438 drivers/gpu/drm/etnaviv/etnaviv_mmu.c 	struct etnaviv_drm_private *priv = gpu->drm->dev_private;
gpu               440 drivers/gpu/drm/etnaviv/etnaviv_mmu.c 	struct device *dev = gpu->drm->dev;
gpu               442 drivers/gpu/drm/etnaviv/etnaviv_mmu.c 	if (gpu->identity.minor_features1 & chipMinorFeatures1_MMU_VERSION)
gpu               447 drivers/gpu/drm/etnaviv/etnaviv_mmu.c 			dev_err(gpu->dev,
gpu               496 drivers/gpu/drm/etnaviv/etnaviv_mmu.c void etnaviv_iommu_global_fini(struct etnaviv_gpu *gpu)
gpu               498 drivers/gpu/drm/etnaviv/etnaviv_mmu.c 	struct etnaviv_drm_private *priv = gpu->drm->dev_private;
gpu                84 drivers/gpu/drm/etnaviv/etnaviv_mmu.h int etnaviv_iommu_global_init(struct etnaviv_gpu *gpu);
gpu                85 drivers/gpu/drm/etnaviv/etnaviv_mmu.h void etnaviv_iommu_global_fini(struct etnaviv_gpu *gpu);
gpu               113 drivers/gpu/drm/etnaviv/etnaviv_mmu.h void etnaviv_iommu_restore(struct etnaviv_gpu *gpu,
gpu                18 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c 	u32 (*sample)(struct etnaviv_gpu *gpu,
gpu                40 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c static u32 perf_reg_read(struct etnaviv_gpu *gpu,
gpu                44 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c 	gpu_write(gpu, domain->profile_config, signal->data);
gpu                46 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c 	return gpu_read(gpu, domain->profile_read);
gpu                49 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c static u32 pipe_reg_read(struct etnaviv_gpu *gpu,
gpu                53 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c 	u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
gpu                57 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c 	for (i = 0; i < gpu->identity.pixel_pipes; i++) {
gpu                60 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c 		gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
gpu                61 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c 		gpu_write(gpu, domain->profile_config, signal->data);
gpu                62 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c 		value += gpu_read(gpu, domain->profile_read);
gpu                68 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c 	gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
gpu                73 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c static u32 hi_total_cycle_read(struct etnaviv_gpu *gpu,
gpu                79 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c 	if (gpu->identity.model == chipModel_GC880 ||
gpu                80 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c 		gpu->identity.model == chipModel_GC2000 ||
gpu                81 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c 		gpu->identity.model == chipModel_GC2100)
gpu                84 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c 	return gpu_read(gpu, reg);
gpu                87 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c static u32 hi_total_idle_cycle_read(struct etnaviv_gpu *gpu,
gpu                93 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c 	if (gpu->identity.model == chipModel_GC880 ||
gpu                94 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c 		gpu->identity.model == chipModel_GC2000 ||
gpu                95 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c 		gpu->identity.model == chipModel_GC2100)
gpu                98 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c 	return gpu_read(gpu, reg);
gpu               430 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c static unsigned int num_pm_domains(const struct etnaviv_gpu *gpu)
gpu               437 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c 		if (gpu->identity.features & meta->feature)
gpu               444 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c static const struct etnaviv_pm_domain *pm_domain(const struct etnaviv_gpu *gpu,
gpu               453 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c 		if (!(gpu->identity.features & meta->feature))
gpu               467 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c int etnaviv_pm_query_dom(struct etnaviv_gpu *gpu,
gpu               470 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c 	const unsigned int nr_domains = num_pm_domains(gpu);
gpu               476 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c 	dom = pm_domain(gpu, domain->iter);
gpu               491 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c int etnaviv_pm_query_sig(struct etnaviv_gpu *gpu,
gpu               494 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c 	const unsigned int nr_domains = num_pm_domains(gpu);
gpu               501 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c 	dom = pm_domain(gpu, signal->domain);
gpu               537 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c void etnaviv_perfmon_process(struct etnaviv_gpu *gpu,
gpu               548 drivers/gpu/drm/etnaviv/etnaviv_perfmon.c 	val = sig->sample(gpu, dom, sig);
gpu                26 drivers/gpu/drm/etnaviv/etnaviv_perfmon.h int etnaviv_pm_query_dom(struct etnaviv_gpu *gpu,
gpu                29 drivers/gpu/drm/etnaviv/etnaviv_perfmon.h int etnaviv_pm_query_sig(struct etnaviv_gpu *gpu,
gpu                35 drivers/gpu/drm/etnaviv/etnaviv_perfmon.h void etnaviv_perfmon_process(struct etnaviv_gpu *gpu,
gpu                80 drivers/gpu/drm/etnaviv/etnaviv_sched.c 		dev_dbg(submit->gpu->dev, "skipping bad job\n");
gpu                88 drivers/gpu/drm/etnaviv/etnaviv_sched.c 	struct etnaviv_gpu *gpu = submit->gpu;
gpu               104 drivers/gpu/drm/etnaviv/etnaviv_sched.c 	dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
gpu               105 drivers/gpu/drm/etnaviv/etnaviv_sched.c 	change = dma_addr - gpu->hangcheck_dma_addr;
gpu               107 drivers/gpu/drm/etnaviv/etnaviv_sched.c 		gpu->hangcheck_dma_addr = dma_addr;
gpu               112 drivers/gpu/drm/etnaviv/etnaviv_sched.c 	drm_sched_stop(&gpu->sched, sched_job);
gpu               119 drivers/gpu/drm/etnaviv/etnaviv_sched.c 	etnaviv_gpu_recover_hang(gpu);
gpu               121 drivers/gpu/drm/etnaviv/etnaviv_sched.c 	drm_sched_resubmit_jobs(&gpu->sched);
gpu               124 drivers/gpu/drm/etnaviv/etnaviv_sched.c 	drm_sched_start(&gpu->sched, true);
gpu               153 drivers/gpu/drm/etnaviv/etnaviv_sched.c 	mutex_lock(&submit->gpu->fence_lock);
gpu               161 drivers/gpu/drm/etnaviv/etnaviv_sched.c 	submit->out_fence_id = idr_alloc_cyclic(&submit->gpu->fence_idr,
gpu               176 drivers/gpu/drm/etnaviv/etnaviv_sched.c 	mutex_unlock(&submit->gpu->fence_lock);
gpu               181 drivers/gpu/drm/etnaviv/etnaviv_sched.c int etnaviv_sched_init(struct etnaviv_gpu *gpu)
gpu               185 drivers/gpu/drm/etnaviv/etnaviv_sched.c 	ret = drm_sched_init(&gpu->sched, &etnaviv_sched_ops,
gpu               187 drivers/gpu/drm/etnaviv/etnaviv_sched.c 			     msecs_to_jiffies(500), dev_name(gpu->dev));
gpu               194 drivers/gpu/drm/etnaviv/etnaviv_sched.c void etnaviv_sched_fini(struct etnaviv_gpu *gpu)
gpu               196 drivers/gpu/drm/etnaviv/etnaviv_sched.c 	drm_sched_fini(&gpu->sched);
gpu                19 drivers/gpu/drm/etnaviv/etnaviv_sched.h int etnaviv_sched_init(struct etnaviv_gpu *gpu);
gpu                20 drivers/gpu/drm/etnaviv/etnaviv_sched.h void etnaviv_sched_fini(struct etnaviv_gpu *gpu);
gpu               711 drivers/gpu/drm/i915/i915_debugfs.c 	struct i915_gpu_state *gpu;
gpu               714 drivers/gpu/drm/i915/i915_debugfs.c 	gpu = NULL;
gpu               716 drivers/gpu/drm/i915/i915_debugfs.c 		gpu = i915_capture_gpu_state(i915);
gpu               717 drivers/gpu/drm/i915/i915_debugfs.c 	if (IS_ERR(gpu))
gpu               718 drivers/gpu/drm/i915/i915_debugfs.c 		return PTR_ERR(gpu);
gpu               720 drivers/gpu/drm/i915/i915_debugfs.c 	file->private_data = gpu;
gpu               207 drivers/gpu/drm/i915/i915_gpu_error.h i915_gpu_state_get(struct i915_gpu_state *gpu)
gpu               209 drivers/gpu/drm/i915/i915_gpu_error.h 	kref_get(&gpu->ref);
gpu               210 drivers/gpu/drm/i915/i915_gpu_error.h 	return gpu;
gpu               217 drivers/gpu/drm/i915/i915_gpu_error.h static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
gpu               219 drivers/gpu/drm/i915/i915_gpu_error.h 	if (gpu)
gpu               220 drivers/gpu/drm/i915/i915_gpu_error.h 		kref_put(&gpu->ref, __i915_gpu_state_free);
gpu               518 drivers/gpu/drm/i915/i915_sysfs.c 	struct i915_gpu_state *gpu;
gpu               521 drivers/gpu/drm/i915/i915_sysfs.c 	gpu = i915_first_error_state(i915);
gpu               522 drivers/gpu/drm/i915/i915_sysfs.c 	if (IS_ERR(gpu)) {
gpu               523 drivers/gpu/drm/i915/i915_sysfs.c 		ret = PTR_ERR(gpu);
gpu               524 drivers/gpu/drm/i915/i915_sysfs.c 	} else if (gpu) {
gpu               525 drivers/gpu/drm/i915/i915_sysfs.c 		ret = i915_gpu_state_copy_to_buffer(gpu, buf, off, count);
gpu               526 drivers/gpu/drm/i915/i915_sysfs.c 		i915_gpu_state_put(gpu);
gpu               990 drivers/gpu/drm/i915/i915_trace.h #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/i915
gpu                10 drivers/gpu/drm/msm/adreno/a2xx_gpu.c static void a2xx_dump(struct msm_gpu *gpu);
gpu                11 drivers/gpu/drm/msm/adreno/a2xx_gpu.c static bool a2xx_idle(struct msm_gpu *gpu);
gpu                13 drivers/gpu/drm/msm/adreno/a2xx_gpu.c static bool a2xx_me_init(struct msm_gpu *gpu)
gpu                15 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	struct msm_ringbuffer *ring = gpu->rb[0];
gpu                56 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu->funcs->flush(gpu, ring);
gpu                57 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	return a2xx_idle(gpu);
gpu                60 drivers/gpu/drm/msm/adreno/a2xx_gpu.c static int a2xx_hw_init(struct msm_gpu *gpu)
gpu                62 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu                67 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	msm_gpummu_params(gpu->aspace->mmu, &pt_base, &tran_error);
gpu                69 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	DBG("%s", gpu->name);
gpu                72 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_AXXX_CP_ME_CNTL, AXXX_CP_ME_CNTL_HALT);
gpu                74 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE1, 0xfffffffe);
gpu                75 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE2, 0xffffffff);
gpu                78 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 0xffffffff);
gpu                80 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 0x00000000);
gpu                83 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 		gpu_write(gpu, REG_A2XX_SQ_FLOW_CONTROL, 0x18000000);
gpu                86 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_A2XX_RBBM_CNTL, 0x00004442);
gpu                89 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_A2XX_MH_MMU_MPU_BASE, 0x00000000);
gpu                90 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_A2XX_MH_MMU_MPU_END, 0xfffff000);
gpu                92 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_A2XX_MH_MMU_CONFIG, A2XX_MH_MMU_CONFIG_MMU_ENABLE |
gpu               106 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_A2XX_MH_MMU_VA_RANGE, SZ_16M |
gpu               109 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_A2XX_MH_MMU_PT_BASE, pt_base);
gpu               110 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_A2XX_MH_MMU_TRAN_ERROR, tran_error);
gpu               112 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_A2XX_MH_MMU_INVALIDATE,
gpu               116 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_A2XX_MH_ARBITER_CONFIG,
gpu               131 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 		gpu_write(gpu, REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1, 0x00032f07);
gpu               133 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_A2XX_SQ_VS_PROGRAM, 0x00000000);
gpu               134 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_A2XX_SQ_PS_PROGRAM, 0x00000000);
gpu               136 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE1, 0); /* 0x200 for msm8960? */
gpu               137 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE2, 0); /* 0x80/0x1a0 for a22x? */
gpu               140 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_A2XX_RBBM_DEBUG, 0x00080000);
gpu               142 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_A2XX_RBBM_INT_CNTL,
gpu               144 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_AXXX_CP_INT_CNTL,
gpu               152 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_A2XX_SQ_INT_CNTL, 0);
gpu               153 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_A2XX_MH_INTERRUPT_MASK,
gpu               161 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_A2XX_RB_EDRAM_INFO, i);
gpu               163 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	ret = adreno_hw_init(gpu);
gpu               178 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_AXXX_CP_DEBUG,
gpu               180 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_AXXX_CP_ME_RAM_WADDR, 0);
gpu               182 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 		gpu_write(gpu, REG_AXXX_CP_ME_RAM_DATA, ptr[i]);
gpu               189 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_A2XX_CP_PFP_UCODE_ADDR, 0);
gpu               191 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 		gpu_write(gpu, REG_A2XX_CP_PFP_UCODE_DATA, ptr[i]);
gpu               193 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS, 0x000C0804);
gpu               196 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_AXXX_CP_ME_CNTL, 0);
gpu               198 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	return a2xx_me_init(gpu) ? 0 : -EINVAL;
gpu               201 drivers/gpu/drm/msm/adreno/a2xx_gpu.c static void a2xx_recover(struct msm_gpu *gpu)
gpu               205 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	adreno_dump_info(gpu);
gpu               209 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 			gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i));
gpu               214 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 		a2xx_dump(gpu);
gpu               216 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 1);
gpu               217 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_read(gpu, REG_A2XX_RBBM_SOFT_RESET);
gpu               218 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 0);
gpu               219 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	adreno_recover(gpu);
gpu               222 drivers/gpu/drm/msm/adreno/a2xx_gpu.c static void a2xx_destroy(struct msm_gpu *gpu)
gpu               224 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               227 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	DBG("%s", gpu->name);
gpu               234 drivers/gpu/drm/msm/adreno/a2xx_gpu.c static bool a2xx_idle(struct msm_gpu *gpu)
gpu               237 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	if (!adreno_idle(gpu, gpu->rb[0]))
gpu               241 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	if (spin_until(!(gpu_read(gpu, REG_A2XX_RBBM_STATUS) &
gpu               243 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 		DRM_ERROR("%s: timeout waiting for GPU to idle!\n", gpu->name);
gpu               252 drivers/gpu/drm/msm/adreno/a2xx_gpu.c static irqreturn_t a2xx_irq(struct msm_gpu *gpu)
gpu               256 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	mstatus = gpu_read(gpu, REG_A2XX_MASTER_INT_SIGNAL);
gpu               259 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 		status = gpu_read(gpu, REG_A2XX_MH_INTERRUPT_STATUS);
gpu               261 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 		dev_warn(gpu->dev->dev, "MH_INT: %08X\n", status);
gpu               262 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 		dev_warn(gpu->dev->dev, "MMU_PAGE_FAULT: %08X\n",
gpu               263 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 			gpu_read(gpu, REG_A2XX_MH_MMU_PAGE_FAULT));
gpu               265 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 		gpu_write(gpu, REG_A2XX_MH_INTERRUPT_CLEAR, status);
gpu               269 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 		status = gpu_read(gpu, REG_AXXX_CP_INT_STATUS);
gpu               273 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 			dev_warn(gpu->dev->dev, "CP_INT: %08X\n", status);
gpu               275 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 		gpu_write(gpu, REG_AXXX_CP_INT_ACK, status);
gpu               279 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 		status = gpu_read(gpu, REG_A2XX_RBBM_INT_STATUS);
gpu               281 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 		dev_warn(gpu->dev->dev, "RBBM_INT: %08X\n", status);
gpu               283 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 		gpu_write(gpu, REG_A2XX_RBBM_INT_ACK, status);
gpu               286 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	msm_gpu_retire(gpu);
gpu               383 drivers/gpu/drm/msm/adreno/a2xx_gpu.c static void a2xx_dump(struct msm_gpu *gpu)
gpu               386 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 			gpu_read(gpu, REG_A2XX_RBBM_STATUS));
gpu               387 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	adreno_dump(gpu);
gpu               390 drivers/gpu/drm/msm/adreno/a2xx_gpu.c static struct msm_gpu_state *a2xx_gpu_state_get(struct msm_gpu *gpu)
gpu               397 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	adreno_gpu_state_get(gpu, state);
gpu               399 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	state->rbbm_status = gpu_read(gpu, REG_A2XX_RBBM_STATUS);
gpu               443 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	struct msm_gpu *gpu;
gpu               461 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu = &adreno_gpu->base;
gpu               463 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu->perfcntrs = perfcntrs;
gpu               464 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs);
gpu               479 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	if (!gpu->aspace) {
gpu               485 drivers/gpu/drm/msm/adreno/a2xx_gpu.c 	return gpu;
gpu                32 drivers/gpu/drm/msm/adreno/a3xx_gpu.c static void a3xx_dump(struct msm_gpu *gpu);
gpu                33 drivers/gpu/drm/msm/adreno/a3xx_gpu.c static bool a3xx_idle(struct msm_gpu *gpu);
gpu                35 drivers/gpu/drm/msm/adreno/a3xx_gpu.c static bool a3xx_me_init(struct msm_gpu *gpu)
gpu                37 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	struct msm_ringbuffer *ring = gpu->rb[0];
gpu                58 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu->funcs->flush(gpu, ring);
gpu                59 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	return a3xx_idle(gpu);
gpu                62 drivers/gpu/drm/msm/adreno/a3xx_gpu.c static int a3xx_hw_init(struct msm_gpu *gpu)
gpu                64 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu                69 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	DBG("%s", gpu->name);
gpu                73 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010);
gpu                74 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x10101010);
gpu                75 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x10101010);
gpu                76 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x10101010);
gpu                77 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303);
gpu                78 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x10101010);
gpu                79 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x10101010);
gpu                81 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x0000ff);
gpu                83 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030);
gpu                85 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c);
gpu                86 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c);
gpu                88 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
gpu                89 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0000000a);
gpu                90 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x0000000a);
gpu                93 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010);
gpu                94 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x10101010);
gpu                95 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x10101010);
gpu                96 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x10101010);
gpu                97 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303);
gpu                98 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x10101010);
gpu                99 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x10101010);
gpu               101 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x0000ff);
gpu               103 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030);
gpu               105 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c);
gpu               106 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c);
gpu               108 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x000000ff);
gpu               109 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4);
gpu               118 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x0001003f);
gpu               119 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4);
gpu               121 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x00003f);
gpu               122 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303);
gpu               124 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
gpu               128 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x18181818);
gpu               129 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x18181818);
gpu               130 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x18181818);
gpu               131 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x18181818);
gpu               132 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303);
gpu               133 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x18181818);
gpu               134 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x18181818);
gpu               136 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x00003f);
gpu               138 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030);
gpu               140 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0001);
gpu               142 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003f);
gpu               143 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003f003f);
gpu               145 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x0001003f);
gpu               146 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4);
gpu               150 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_VBIF_CLKON, 0x00000001);
gpu               157 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_A3XX_RBBM_GPU_BUSY_MASKED, 0xffffffff);
gpu               160 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_A3XX_RBBM_SP_HYST_CNT, 0x10);
gpu               161 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL, 0x10);
gpu               166 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_A3XX_RBBM_AHB_CTL0, 0x00000001);
gpu               169 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_A3XX_RBBM_AHB_CTL1, 0xa6ffffff);
gpu               172 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_A3XX_RBBM_RBBM_CTL, 0x00030000);
gpu               177 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL, 0x00010fff);
gpu               180 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001);
gpu               184 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);
gpu               186 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfffffff);
gpu               188 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);
gpu               190 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbffcffff);
gpu               193 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_RBBM_GPR0_CTL, 0x05515455);
gpu               195 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_RBBM_GPR0_CTL, 0x00000000);
gpu               199 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_RB_GMEM_BASE_ADDR,
gpu               204 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_A3XX_RBBM_PERFCTR_CTL, 0x01);
gpu               207 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	for (i = 0; i < gpu->num_perfcntrs; i++) {
gpu               208 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		const struct msm_gpu_perfcntr *perfcntr = &gpu->perfcntrs[i];
gpu               209 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, perfcntr->select_reg, perfcntr->select_val);
gpu               212 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_A3XX_RBBM_INT_0_MASK, A3XX_INT0_MASK);
gpu               214 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	ret = adreno_hw_init(gpu);
gpu               219 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_A3XX_CP_PROTECT_CTRL, 0x00000007);
gpu               222 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_A3XX_CP_PROTECT(0), 0x63000040);
gpu               223 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_A3XX_CP_PROTECT(1), 0x62000080);
gpu               224 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_A3XX_CP_PROTECT(2), 0x600000cc);
gpu               225 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_A3XX_CP_PROTECT(3), 0x60000108);
gpu               226 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_A3XX_CP_PROTECT(4), 0x64000140);
gpu               227 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_A3XX_CP_PROTECT(5), 0x66000400);
gpu               230 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_A3XX_CP_PROTECT(6), 0x65000700);
gpu               231 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_A3XX_CP_PROTECT(7), 0x610007d8);
gpu               232 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_A3XX_CP_PROTECT(8), 0x620007e0);
gpu               233 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_A3XX_CP_PROTECT(9), 0x61001178);
gpu               234 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_A3XX_CP_PROTECT(10), 0x64001180);
gpu               237 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_A3XX_CP_PROTECT(11), 0x60003300);
gpu               240 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_A3XX_CP_PROTECT(12), 0x6b00c000);
gpu               253 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_AXXX_CP_DEBUG,
gpu               256 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_AXXX_CP_ME_RAM_WADDR, 0);
gpu               258 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_AXXX_CP_ME_RAM_DATA, ptr[i]);
gpu               265 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_ADDR, 0);
gpu               267 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_DATA, ptr[i]);
gpu               272 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS,
gpu               282 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS, 0x003e2008);
gpu               286 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_AXXX_CP_ME_CNTL, 0);
gpu               288 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	return a3xx_me_init(gpu) ? 0 : -EINVAL;
gpu               291 drivers/gpu/drm/msm/adreno/a3xx_gpu.c static void a3xx_recover(struct msm_gpu *gpu)
gpu               295 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	adreno_dump_info(gpu);
gpu               299 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 			gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i));
gpu               304 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		a3xx_dump(gpu);
gpu               306 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_A3XX_RBBM_SW_RESET_CMD, 1);
gpu               307 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_read(gpu, REG_A3XX_RBBM_SW_RESET_CMD);
gpu               308 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_A3XX_RBBM_SW_RESET_CMD, 0);
gpu               309 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	adreno_recover(gpu);
gpu               312 drivers/gpu/drm/msm/adreno/a3xx_gpu.c static void a3xx_destroy(struct msm_gpu *gpu)
gpu               314 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               317 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	DBG("%s", gpu->name);
gpu               329 drivers/gpu/drm/msm/adreno/a3xx_gpu.c static bool a3xx_idle(struct msm_gpu *gpu)
gpu               332 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	if (!adreno_idle(gpu, gpu->rb[0]))
gpu               336 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	if (spin_until(!(gpu_read(gpu, REG_A3XX_RBBM_STATUS) &
gpu               338 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 		DRM_ERROR("%s: timeout waiting for GPU to idle!\n", gpu->name);
gpu               347 drivers/gpu/drm/msm/adreno/a3xx_gpu.c static irqreturn_t a3xx_irq(struct msm_gpu *gpu)
gpu               351 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	status = gpu_read(gpu, REG_A3XX_RBBM_INT_0_STATUS);
gpu               352 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	DBG("%s: %08x", gpu->name, status);
gpu               356 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu_write(gpu, REG_A3XX_RBBM_INT_CLEAR_CMD, status);
gpu               358 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	msm_gpu_retire(gpu);
gpu               402 drivers/gpu/drm/msm/adreno/a3xx_gpu.c static void a3xx_dump(struct msm_gpu *gpu)
gpu               405 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 			gpu_read(gpu, REG_A3XX_RBBM_STATUS));
gpu               406 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	adreno_dump(gpu);
gpu               409 drivers/gpu/drm/msm/adreno/a3xx_gpu.c static struct msm_gpu_state *a3xx_gpu_state_get(struct msm_gpu *gpu)
gpu               416 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	adreno_gpu_state_get(gpu, state);
gpu               418 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	state->rbbm_status = gpu_read(gpu, REG_A3XX_RBBM_STATUS);
gpu               465 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	struct msm_gpu *gpu;
gpu               483 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu = &adreno_gpu->base;
gpu               485 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu->perfcntrs = perfcntrs;
gpu               486 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs);
gpu               510 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	if (!gpu->aspace) {
gpu               523 drivers/gpu/drm/msm/adreno/a3xx_gpu.c 	return gpu;
gpu                25 drivers/gpu/drm/msm/adreno/a4xx_gpu.c static void a4xx_dump(struct msm_gpu *gpu);
gpu                26 drivers/gpu/drm/msm/adreno/a4xx_gpu.c static bool a4xx_idle(struct msm_gpu *gpu);
gpu                32 drivers/gpu/drm/msm/adreno/a4xx_gpu.c static void a4xx_enable_hwcg(struct msm_gpu *gpu)
gpu                34 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu                37 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TP(i), 0x02222202);
gpu                39 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_TP(i), 0x00002222);
gpu                41 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_TP(i), 0x0E739CE7);
gpu                43 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TP(i), 0x00111111);
gpu                45 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_SP(i), 0x22222222);
gpu                47 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_SP(i), 0x00222222);
gpu                49 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_SP(i), 0x00000104);
gpu                51 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_SP(i), 0x00000081);
gpu                52 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_UCHE, 0x22222222);
gpu                53 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_UCHE, 0x02222222);
gpu                54 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL3_UCHE, 0x00000000);
gpu                55 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL4_UCHE, 0x00000000);
gpu                56 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_UCHE, 0x00004444);
gpu                57 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_UCHE, 0x00001112);
gpu                59 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_RB(i), 0x22222222);
gpu                64 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 			gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_RB(i),
gpu                67 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 			gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_RB(i),
gpu                73 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(i),
gpu                78 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(i),
gpu                83 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(i),
gpu                87 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_MODE_GPC, 0x02222222);
gpu                88 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_GPC, 0x04100104);
gpu                89 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_GPC, 0x00022222);
gpu                90 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM, 0x00000022);
gpu                91 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM, 0x0000010F);
gpu                92 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM, 0x00000022);
gpu                93 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM, 0x00222222);
gpu                94 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00004104);
gpu                95 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00000222);
gpu                96 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_HLSQ , 0x00000000);
gpu                97 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000);
gpu                98 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, 0x00220000);
gpu               102 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0);
gpu               104 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0xAAAAAAAA);
gpu               105 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2, 0);
gpu               109 drivers/gpu/drm/msm/adreno/a4xx_gpu.c static bool a4xx_me_init(struct msm_gpu *gpu)
gpu               111 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	struct msm_ringbuffer *ring = gpu->rb[0];
gpu               132 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu->funcs->flush(gpu, ring);
gpu               133 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	return a4xx_idle(gpu);
gpu               136 drivers/gpu/drm/msm/adreno/a4xx_gpu.c static int a4xx_hw_init(struct msm_gpu *gpu)
gpu               138 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               144 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT, 0x0001001F);
gpu               145 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT_CONF, 0x000000A4);
gpu               146 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000001);
gpu               147 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_VBIF_IN_RD_LIM_CONF0, 0x18181818);
gpu               148 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_VBIF_IN_RD_LIM_CONF1, 0x00000018);
gpu               149 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF0, 0x18181818);
gpu               150 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF1, 0x00000018);
gpu               151 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003);
gpu               153 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000001);
gpu               154 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_VBIF_IN_RD_LIM_CONF0, 0x18181818);
gpu               155 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_VBIF_IN_RD_LIM_CONF1, 0x00000018);
gpu               156 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF0, 0x18181818);
gpu               157 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF1, 0x00000018);
gpu               158 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003);
gpu               164 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_GPU_BUSY_MASKED, 0xffffffff);
gpu               167 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_SP_HYST_CNT, 0x10);
gpu               168 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL, 0x10);
gpu               171 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2, 0x30);
gpu               175 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_AHB_CTL0, 0x00000001);
gpu               178 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_AHB_CTL1, 0xa6ffffff);
gpu               181 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_RBBM_CTL, 0x00000030);
gpu               187 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL,
gpu               190 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RB_GMEM_BASE_ADDR,
gpu               194 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_PERFCTR_CTL, 0x01);
gpu               199 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_CP_PERFCTR_CP_SEL_0, CP_ALWAYS_COUNT);
gpu               202 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_UCHE_CACHE_WAYS_VFD, 0x07);
gpu               205 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_UCHE_TRAP_BASE_LO, 0xffff0000);
gpu               206 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_UCHE_TRAP_BASE_HI, 0xffff0000);
gpu               208 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_CP_DEBUG, (1 << 25) |
gpu               214 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0,
gpu               216 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1,
gpu               220 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	a4xx_enable_hwcg(gpu);
gpu               228 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		val = gpu_read(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ);
gpu               231 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, val);
gpu               235 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_CP_PROTECT_CTRL, 0x00000007);
gpu               238 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_CP_PROTECT(0), 0x62000010);
gpu               239 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_CP_PROTECT(1), 0x63000020);
gpu               240 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_CP_PROTECT(2), 0x64000040);
gpu               241 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_CP_PROTECT(3), 0x65000080);
gpu               242 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_CP_PROTECT(4), 0x66000100);
gpu               243 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_CP_PROTECT(5), 0x64000200);
gpu               246 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_CP_PROTECT(6), 0x67000800);
gpu               247 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_CP_PROTECT(7), 0x64001600);
gpu               251 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_CP_PROTECT(8), 0x60003300);
gpu               254 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_CP_PROTECT(9), 0x60003800);
gpu               257 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_CP_PROTECT(10), 0x61003980);
gpu               260 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_CP_PROTECT(11), 0x6e010000);
gpu               262 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_INT_0_MASK, A4XX_INT0_MASK);
gpu               264 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	ret = adreno_hw_init(gpu);
gpu               272 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_CP_ME_RAM_WADDR, 0);
gpu               274 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_CP_ME_RAM_DATA, ptr[i]);
gpu               281 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_CP_PFP_UCODE_ADDR, 0);
gpu               283 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_CP_PFP_UCODE_DATA, ptr[i]);
gpu               286 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_CP_ME_CNTL, 0);
gpu               288 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	return a4xx_me_init(gpu) ? 0 : -EINVAL;
gpu               291 drivers/gpu/drm/msm/adreno/a4xx_gpu.c static void a4xx_recover(struct msm_gpu *gpu)
gpu               295 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	adreno_dump_info(gpu);
gpu               299 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 			gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i));
gpu               304 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		a4xx_dump(gpu);
gpu               306 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_SW_RESET_CMD, 1);
gpu               307 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_read(gpu, REG_A4XX_RBBM_SW_RESET_CMD);
gpu               308 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_SW_RESET_CMD, 0);
gpu               309 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	adreno_recover(gpu);
gpu               312 drivers/gpu/drm/msm/adreno/a4xx_gpu.c static void a4xx_destroy(struct msm_gpu *gpu)
gpu               314 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               317 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	DBG("%s", gpu->name);
gpu               329 drivers/gpu/drm/msm/adreno/a4xx_gpu.c static bool a4xx_idle(struct msm_gpu *gpu)
gpu               332 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	if (!adreno_idle(gpu, gpu->rb[0]))
gpu               336 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	if (spin_until(!(gpu_read(gpu, REG_A4XX_RBBM_STATUS) &
gpu               338 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		DRM_ERROR("%s: timeout waiting for GPU to idle!\n", gpu->name);
gpu               346 drivers/gpu/drm/msm/adreno/a4xx_gpu.c static irqreturn_t a4xx_irq(struct msm_gpu *gpu)
gpu               350 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	status = gpu_read(gpu, REG_A4XX_RBBM_INT_0_STATUS);
gpu               351 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	DBG("%s: Int status %08x", gpu->name, status);
gpu               354 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		uint32_t reg = gpu_read(gpu, REG_A4XX_CP_PROTECT_STATUS);
gpu               360 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu_write(gpu, REG_A4XX_RBBM_INT_CLEAR_CMD, status);
gpu               362 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	msm_gpu_retire(gpu);
gpu               449 drivers/gpu/drm/msm/adreno/a4xx_gpu.c static struct msm_gpu_state *a4xx_gpu_state_get(struct msm_gpu *gpu)
gpu               456 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	adreno_gpu_state_get(gpu, state);
gpu               458 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	state->rbbm_status = gpu_read(gpu, REG_A4XX_RBBM_STATUS);
gpu               474 drivers/gpu/drm/msm/adreno/a4xx_gpu.c static void a4xx_dump(struct msm_gpu *gpu)
gpu               477 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 			gpu_read(gpu, REG_A4XX_RBBM_STATUS));
gpu               478 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	adreno_dump(gpu);
gpu               481 drivers/gpu/drm/msm/adreno/a4xx_gpu.c static int a4xx_pm_resume(struct msm_gpu *gpu) {
gpu               482 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               485 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	ret = msm_gpu_pm_resume(gpu);
gpu               492 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_RBBM_POWER_CNTL_IP, 0x778000);
gpu               495 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 			reg = gpu_read(gpu, REG_A4XX_RBBM_POWER_STATUS);
gpu               501 drivers/gpu/drm/msm/adreno/a4xx_gpu.c static int a4xx_pm_suspend(struct msm_gpu *gpu) {
gpu               502 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               505 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	ret = msm_gpu_pm_suspend(gpu);
gpu               511 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 		gpu_write(gpu, REG_A4XX_RBBM_POWER_CNTL_IP, 0x778001);
gpu               516 drivers/gpu/drm/msm/adreno/a4xx_gpu.c static int a4xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
gpu               518 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	*value = gpu_read64(gpu, REG_A4XX_RBBM_PERFCTR_CP_0_LO,
gpu               549 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	struct msm_gpu *gpu;
gpu               567 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu = &adreno_gpu->base;
gpu               569 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu->perfcntrs = NULL;
gpu               570 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	gpu->num_perfcntrs = 0;
gpu               594 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	if (!gpu->aspace) {
gpu               607 drivers/gpu/drm/msm/adreno/a4xx_gpu.c 	return gpu;
gpu                14 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c static int pfp_print(struct msm_gpu *gpu, struct drm_printer *p)
gpu                21 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c 		gpu_write(gpu, REG_A5XX_CP_PFP_STAT_ADDR, i);
gpu                23 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c 			gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA));
gpu                29 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c static int me_print(struct msm_gpu *gpu, struct drm_printer *p)
gpu                36 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c 		gpu_write(gpu, REG_A5XX_CP_ME_STAT_ADDR, i);
gpu                38 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c 			gpu_read(gpu, REG_A5XX_CP_ME_STAT_DATA));
gpu                44 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c static int meq_print(struct msm_gpu *gpu, struct drm_printer *p)
gpu                49 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c 	gpu_write(gpu, REG_A5XX_CP_MEQ_DBG_ADDR, 0);
gpu                53 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c 			gpu_read(gpu, REG_A5XX_CP_MEQ_DBG_DATA));
gpu                59 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c static int roq_print(struct msm_gpu *gpu, struct drm_printer *p)
gpu                64 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c 	gpu_write(gpu, REG_A5XX_CP_ROQ_DBG_ADDR, 0);
gpu                70 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c 			val[j] = gpu_read(gpu, REG_A5XX_CP_ROQ_DBG_DATA);
gpu                84 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c 	int (*show)(struct msm_gpu *gpu, struct drm_printer *p) =
gpu                87 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c 	return show(priv->gpu, &p);
gpu               104 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c 	struct msm_gpu *gpu = priv->gpu;
gpu               105 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               126 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c 		msm_gem_unpin_iova(a5xx_gpu->pm4_bo, gpu->aspace);
gpu               132 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c 		msm_gem_unpin_iova(a5xx_gpu->pfp_bo, gpu->aspace);
gpu               137 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c 	gpu->needs_hw_init = true;
gpu               139 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c 	pm_runtime_get_sync(&gpu->pdev->dev);
gpu               140 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c 	gpu->funcs->recover(gpu);
gpu               142 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c 	pm_runtime_put_sync(&gpu->pdev->dev);
gpu               151 drivers/gpu/drm/msm/adreno/a5xx_debugfs.c int a5xx_debugfs_init(struct msm_gpu *gpu, struct drm_minor *minor)
gpu                17 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static void a5xx_dump(struct msm_gpu *gpu);
gpu                21 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
gpu                23 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu                43 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr);
gpu                46 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit,
gpu                49 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	struct msm_drm_private *priv = gpu->dev->dev_private;
gpu                94 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	a5xx_flush(gpu, ring);
gpu                95 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	a5xx_preempt_trigger(gpu);
gpu               101 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	a5xx_idle(gpu, ring);
gpu               103 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	msm_gpu_retire(gpu);
gpu               106 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
gpu               109 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               111 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	struct msm_drm_private *priv = gpu->dev->dev_private;
gpu               117 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		a5xx_submit_in_rb(gpu, submit, ctx);
gpu               208 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	a5xx_flush(gpu, ring);
gpu               211 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	a5xx_preempt_trigger(gpu);
gpu               312 drivers/gpu/drm/msm/adreno/a5xx_gpu.c void a5xx_set_hwcg(struct msm_gpu *gpu, bool state)
gpu               314 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               318 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_write(gpu, a5xx_hwcg[i].offset,
gpu               322 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_write(gpu, REG_A5XX_RBBM_CLOCK_DELAY_GPMU, state ? 0x00000770 : 0);
gpu               323 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_write(gpu, REG_A5XX_RBBM_CLOCK_HYST_GPMU, state ? 0x00000004 : 0);
gpu               326 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_RBBM_CLOCK_CNTL, state ? 0xAAA8AA00 : 0);
gpu               327 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_RBBM_ISDB_CNT, state ? 0x182 : 0x180);
gpu               330 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static int a5xx_me_init(struct msm_gpu *gpu)
gpu               332 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               333 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	struct msm_ringbuffer *ring = gpu->rb[0];
gpu               364 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu->funcs->flush(gpu, ring);
gpu               365 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	return a5xx_idle(gpu, ring) ? 0 : -EINVAL;
gpu               368 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static int a5xx_preempt_start(struct msm_gpu *gpu)
gpu               370 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               372 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	struct msm_ringbuffer *ring = gpu->rb[0];
gpu               374 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	if (gpu->nr_rings == 1)
gpu               406 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu->funcs->flush(gpu, ring);
gpu               408 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	return a5xx_idle(gpu, ring) ? 0 : -EINVAL;
gpu               411 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static int a5xx_ucode_init(struct msm_gpu *gpu)
gpu               413 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               418 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		a5xx_gpu->pm4_bo = adreno_fw_create_bo(gpu,
gpu               425 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 			DRM_DEV_ERROR(gpu->dev->dev, "could not allocate PM4: %d\n",
gpu               434 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		a5xx_gpu->pfp_bo = adreno_fw_create_bo(gpu,
gpu               440 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 			DRM_DEV_ERROR(gpu->dev->dev, "could not allocate PFP: %d\n",
gpu               448 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write64(gpu, REG_A5XX_CP_ME_INSTR_BASE_LO,
gpu               451 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write64(gpu, REG_A5XX_CP_PFP_INSTR_BASE_LO,
gpu               459 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static int a5xx_zap_shader_resume(struct msm_gpu *gpu)
gpu               466 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 			gpu->name, ret);
gpu               471 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static int a5xx_zap_shader_init(struct msm_gpu *gpu)
gpu               481 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		return a5xx_zap_shader_resume(gpu);
gpu               483 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	ret = adreno_zap_shader_load(gpu, GPU_PAS_ID);
gpu               502 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static int a5xx_hw_init(struct msm_gpu *gpu)
gpu               504 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               507 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003);
gpu               510 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_write(gpu, REG_A5XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009);
gpu               513 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xFFFFFFFF);
gpu               516 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL0, 0x00000001);
gpu               524 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11,
gpu               526 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12,
gpu               528 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13,
gpu               530 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14,
gpu               532 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15,
gpu               534 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16,
gpu               536 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17,
gpu               538 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18,
gpu               543 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL,
gpu               547 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_CNTL, 0x01);
gpu               550 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT);
gpu               553 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0, 6);
gpu               556 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_UCHE_CACHE_WAYS, 0x02);
gpu               559 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_LO, 0xFFFF0000);
gpu               560 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_HI, 0x0001FFFF);
gpu               561 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_LO, 0xFFFF0000);
gpu               562 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_HI, 0x0001FFFF);
gpu               565 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_LO, 0x00100000);
gpu               566 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_HI, 0x00000000);
gpu               567 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_LO,
gpu               569 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x00000000);
gpu               571 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x40);
gpu               573 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x40);
gpu               575 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400);
gpu               576 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x80000060);
gpu               577 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x40201B16);
gpu               579 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, (0x400 << 11 | 0x300 << 22));
gpu               582 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_rmw(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0, (1 << 8));
gpu               584 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0xc0200100);
gpu               587 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_CP_CHICKEN_DBG, 0x02000000);
gpu               590 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL1, 0xA6FFFFFF);
gpu               593 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	a5xx_set_hwcg(gpu, true);
gpu               595 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL2, 0x0000003F);
gpu               598 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_TPL1_MODE_CNTL, 2 << 7);
gpu               599 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_RB_MODE_CNTL, 2 << 1);
gpu               601 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_write(gpu, REG_A5XX_UCHE_DBG_ECO_CNTL_2, 2);
gpu               604 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_CP_PROTECT_CNTL, 0x00000007);
gpu               607 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_CP_PROTECT(0), ADRENO_PROTECT_RW(0x04, 4));
gpu               608 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_CP_PROTECT(1), ADRENO_PROTECT_RW(0x08, 8));
gpu               609 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_CP_PROTECT(2), ADRENO_PROTECT_RW(0x10, 16));
gpu               610 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_CP_PROTECT(3), ADRENO_PROTECT_RW(0x20, 32));
gpu               611 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_CP_PROTECT(4), ADRENO_PROTECT_RW(0x40, 64));
gpu               612 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_CP_PROTECT(5), ADRENO_PROTECT_RW(0x80, 64));
gpu               615 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_CP_PROTECT(6),
gpu               618 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_CP_PROTECT(7),
gpu               622 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_CP_PROTECT(8), ADRENO_PROTECT_RW(0x800, 64));
gpu               623 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_CP_PROTECT(9), ADRENO_PROTECT_RW(0x840, 8));
gpu               624 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_CP_PROTECT(10), ADRENO_PROTECT_RW(0x880, 32));
gpu               625 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_CP_PROTECT(11), ADRENO_PROTECT_RW(0xAA0, 1));
gpu               628 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_CP_PROTECT(12), ADRENO_PROTECT_RW(0xCC0, 1));
gpu               629 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_CP_PROTECT(13), ADRENO_PROTECT_RW(0xCF0, 2));
gpu               632 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_CP_PROTECT(14), ADRENO_PROTECT_RW(0xE68, 8));
gpu               633 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_CP_PROTECT(15), ADRENO_PROTECT_RW(0xE70, 4));
gpu               636 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_CP_PROTECT(16), ADRENO_PROTECT_RW(0xE80, 16));
gpu               639 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_write(gpu, REG_A5XX_CP_PROTECT(17),
gpu               642 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_CNTL, 0);
gpu               648 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write64(gpu, REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO,
gpu               650 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000);
gpu               653 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_CP_ADDR_MODE_CNTL, 0x1);
gpu               654 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_VSC_ADDR_MODE_CNTL, 0x1);
gpu               655 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_GRAS_ADDR_MODE_CNTL, 0x1);
gpu               656 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_RB_ADDR_MODE_CNTL, 0x1);
gpu               657 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_PC_ADDR_MODE_CNTL, 0x1);
gpu               658 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_HLSQ_ADDR_MODE_CNTL, 0x1);
gpu               659 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_VFD_ADDR_MODE_CNTL, 0x1);
gpu               660 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_VPC_ADDR_MODE_CNTL, 0x1);
gpu               661 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_UCHE_ADDR_MODE_CNTL, 0x1);
gpu               662 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_SP_ADDR_MODE_CNTL, 0x1);
gpu               663 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_TPL1_ADDR_MODE_CNTL, 0x1);
gpu               664 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);
gpu               672 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_rmw(gpu, REG_A5XX_VPC_DBG_ECO_CNTL, 0, BIT(23));
gpu               673 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_rmw(gpu, REG_A5XX_HLSQ_DBG_ECO_CNTL, BIT(18), 0);
gpu               676 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	ret = adreno_hw_init(gpu);
gpu               680 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	a5xx_preempt_hw_init(gpu);
gpu               682 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	a5xx_gpmu_ucode_init(gpu);
gpu               684 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	ret = a5xx_ucode_init(gpu);
gpu               689 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_RBBM_INT_0_MASK, A5XX_INT_MASK);
gpu               692 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_CP_PFP_ME_CNTL, 0);
gpu               693 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	ret = a5xx_me_init(gpu);
gpu               697 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	ret = a5xx_power_init(gpu);
gpu               706 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		OUT_PKT7(gpu->rb[0], CP_EVENT_WRITE, 1);
gpu               707 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		OUT_RING(gpu->rb[0], 0x0F);
gpu               709 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu->funcs->flush(gpu, gpu->rb[0]);
gpu               710 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		if (!a5xx_idle(gpu, gpu->rb[0]))
gpu               721 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	ret = a5xx_zap_shader_init(gpu);
gpu               723 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1);
gpu               724 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		OUT_RING(gpu->rb[0], 0x00000000);
gpu               726 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu->funcs->flush(gpu, gpu->rb[0]);
gpu               727 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		if (!a5xx_idle(gpu, gpu->rb[0]))
gpu               736 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		dev_warn_once(gpu->dev->dev,
gpu               738 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_write(gpu, REG_A5XX_RBBM_SECVID_TRUST_CNTL, 0x0);
gpu               744 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	a5xx_preempt_start(gpu);
gpu               749 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static void a5xx_recover(struct msm_gpu *gpu)
gpu               753 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	adreno_dump_info(gpu);
gpu               757 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 			gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(i)));
gpu               761 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		a5xx_dump(gpu);
gpu               763 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_RBBM_SW_RESET_CMD, 1);
gpu               764 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_read(gpu, REG_A5XX_RBBM_SW_RESET_CMD);
gpu               765 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_RBBM_SW_RESET_CMD, 0);
gpu               766 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	adreno_recover(gpu);
gpu               769 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static void a5xx_destroy(struct msm_gpu *gpu)
gpu               771 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               774 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	DBG("%s", gpu->name);
gpu               776 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	a5xx_preempt_fini(gpu);
gpu               779 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		msm_gem_unpin_iova(a5xx_gpu->pm4_bo, gpu->aspace);
gpu               784 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		msm_gem_unpin_iova(a5xx_gpu->pfp_bo, gpu->aspace);
gpu               789 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		msm_gem_unpin_iova(a5xx_gpu->gpmu_bo, gpu->aspace);
gpu               797 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static inline bool _a5xx_check_idle(struct msm_gpu *gpu)
gpu               799 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	if (gpu_read(gpu, REG_A5XX_RBBM_STATUS) & ~A5XX_RBBM_STATUS_HI_BUSY)
gpu               806 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	return !(gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS) &
gpu               810 drivers/gpu/drm/msm/adreno/a5xx_gpu.c bool a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
gpu               812 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               821 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	if (!adreno_idle(gpu, ring))
gpu               824 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	if (spin_until(_a5xx_check_idle(gpu))) {
gpu               826 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 			gpu->name, __builtin_return_address(0),
gpu               827 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 			gpu_read(gpu, REG_A5XX_RBBM_STATUS),
gpu               828 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 			gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS),
gpu               829 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 			gpu_read(gpu, REG_A5XX_CP_RB_RPTR),
gpu               830 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 			gpu_read(gpu, REG_A5XX_CP_RB_WPTR));
gpu               839 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	struct msm_gpu *gpu = arg;
gpu               842 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 			gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(4)),
gpu               843 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 			gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(5)),
gpu               844 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 			gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(6)),
gpu               845 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 			gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(7)));
gpu               850 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static void a5xx_cp_err_irq(struct msm_gpu *gpu)
gpu               852 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	u32 status = gpu_read(gpu, REG_A5XX_CP_INTERRUPT_STATUS);
gpu               857 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_write(gpu, REG_A5XX_CP_PFP_STAT_ADDR, 0);
gpu               864 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA);
gpu               865 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		val = gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA);
gpu               867 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		dev_err_ratelimited(gpu->dev->dev, "CP | opcode error | possible opcode=0x%8.8X\n",
gpu               872 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		dev_err_ratelimited(gpu->dev->dev, "CP | HW fault | status=0x%8.8X\n",
gpu               873 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 			gpu_read(gpu, REG_A5XX_CP_HW_FAULT));
gpu               876 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		dev_err_ratelimited(gpu->dev->dev, "CP | DMA error\n");
gpu               879 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		u32 val = gpu_read(gpu, REG_A5XX_CP_PROTECT_STATUS);
gpu               881 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		dev_err_ratelimited(gpu->dev->dev,
gpu               888 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		u32 status = gpu_read(gpu, REG_A5XX_CP_AHB_FAULT);
gpu               894 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		dev_err_ratelimited(gpu->dev->dev,
gpu               901 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static void a5xx_rbbm_err_irq(struct msm_gpu *gpu, u32 status)
gpu               904 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		u32 val = gpu_read(gpu, REG_A5XX_RBBM_AHB_ERROR_STATUS);
gpu               906 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		dev_err_ratelimited(gpu->dev->dev,
gpu               913 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_write(gpu, REG_A5XX_RBBM_AHB_CMD, (1 << 4));
gpu               916 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_write(gpu, REG_A5XX_RBBM_INT_CLEAR_CMD,
gpu               921 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		dev_err_ratelimited(gpu->dev->dev, "RBBM | AHB transfer timeout\n");
gpu               924 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		dev_err_ratelimited(gpu->dev->dev, "RBBM | ME master split | status=0x%X\n",
gpu               925 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 			gpu_read(gpu, REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS));
gpu               928 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		dev_err_ratelimited(gpu->dev->dev, "RBBM | PFP master split | status=0x%X\n",
gpu               929 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 			gpu_read(gpu, REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS));
gpu               932 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		dev_err_ratelimited(gpu->dev->dev, "RBBM | ETS master split | status=0x%X\n",
gpu               933 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 			gpu_read(gpu, REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS));
gpu               936 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		dev_err_ratelimited(gpu->dev->dev, "RBBM | ATB ASYNC overflow\n");
gpu               939 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		dev_err_ratelimited(gpu->dev->dev, "RBBM | ATB bus overflow\n");
gpu               942 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static void a5xx_uche_err_irq(struct msm_gpu *gpu)
gpu               944 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	uint64_t addr = (uint64_t) gpu_read(gpu, REG_A5XX_UCHE_TRAP_LOG_HI);
gpu               946 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	addr |= gpu_read(gpu, REG_A5XX_UCHE_TRAP_LOG_LO);
gpu               948 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	dev_err_ratelimited(gpu->dev->dev, "UCHE | Out of bounds access | addr=0x%llX\n",
gpu               952 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static void a5xx_gpmu_err_irq(struct msm_gpu *gpu)
gpu               954 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	dev_err_ratelimited(gpu->dev->dev, "GPMU | voltage droop\n");
gpu               957 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static void a5xx_fault_detect_irq(struct msm_gpu *gpu)
gpu               959 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	struct drm_device *dev = gpu->dev;
gpu               961 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
gpu               965 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_read(gpu, REG_A5XX_RBBM_STATUS),
gpu               966 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_read(gpu, REG_A5XX_CP_RB_RPTR),
gpu               967 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_read(gpu, REG_A5XX_CP_RB_WPTR),
gpu               968 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_read64(gpu, REG_A5XX_CP_IB1_BASE, REG_A5XX_CP_IB1_BASE_HI),
gpu               969 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_read(gpu, REG_A5XX_CP_IB1_BUFSZ),
gpu               970 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_read64(gpu, REG_A5XX_CP_IB2_BASE, REG_A5XX_CP_IB2_BASE_HI),
gpu               971 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_read(gpu, REG_A5XX_CP_IB2_BUFSZ));
gpu               974 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	del_timer(&gpu->hangcheck_timer);
gpu               976 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	queue_work(priv->wq, &gpu->recover_work);
gpu               987 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static irqreturn_t a5xx_irq(struct msm_gpu *gpu)
gpu               989 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	u32 status = gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS);
gpu               995 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_RBBM_INT_CLEAR_CMD,
gpu              1000 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		a5xx_rbbm_err_irq(gpu, status);
gpu              1003 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		a5xx_cp_err_irq(gpu);
gpu              1006 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		a5xx_fault_detect_irq(gpu);
gpu              1009 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		a5xx_uche_err_irq(gpu);
gpu              1012 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		a5xx_gpmu_err_irq(gpu);
gpu              1015 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		a5xx_preempt_trigger(gpu);
gpu              1016 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		msm_gpu_retire(gpu);
gpu              1020 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		a5xx_preempt_irq(gpu);
gpu              1067 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static void a5xx_dump(struct msm_gpu *gpu)
gpu              1069 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	DRM_DEV_INFO(gpu->dev->dev, "status:   %08x\n",
gpu              1070 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		gpu_read(gpu, REG_A5XX_RBBM_STATUS));
gpu              1071 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	adreno_dump(gpu);
gpu              1074 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static int a5xx_pm_resume(struct msm_gpu *gpu)
gpu              1079 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	ret = msm_gpu_pm_resume(gpu);
gpu              1084 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_GPMU_RBCCU_POWER_CNTL, 0x778000);
gpu              1089 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	ret = spin_usecs(gpu, 20, REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS,
gpu              1093 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 			gpu->name,
gpu              1094 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 			gpu_read(gpu, REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS));
gpu              1099 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_GPMU_SP_POWER_CNTL, 0x778000);
gpu              1100 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	ret = spin_usecs(gpu, 20, REG_A5XX_GPMU_SP_PWR_CLK_STATUS,
gpu              1104 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 			gpu->name);
gpu              1109 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static int a5xx_pm_suspend(struct msm_gpu *gpu)
gpu              1112 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL0, 0xF);
gpu              1113 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	spin_until((gpu_read(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL1) & 0xF) == 0xF);
gpu              1115 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL0, 0);
gpu              1121 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x003C0000);
gpu              1122 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x00000000);
gpu              1124 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	return msm_gpu_pm_suspend(gpu);
gpu              1127 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static int a5xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
gpu              1129 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	*value = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_CP_0_LO,
gpu              1146 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static int a5xx_crashdumper_init(struct msm_gpu *gpu,
gpu              1149 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	dumper->ptr = msm_gem_kernel_new_locked(gpu->dev,
gpu              1150 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		SZ_1M, MSM_BO_UNCACHED, gpu->aspace,
gpu              1159 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static int a5xx_crashdumper_run(struct msm_gpu *gpu,
gpu              1167 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write64(gpu, REG_A5XX_CP_CRASH_SCRIPT_BASE_LO,
gpu              1170 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu_write(gpu, REG_A5XX_CP_CRASH_DUMP_CNTL, 1);
gpu              1172 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	return gpu_poll_timeout(gpu, REG_A5XX_CP_CRASH_DUMP_CNTL, val,
gpu              1203 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static void a5xx_gpu_state_get_hlsq_regs(struct msm_gpu *gpu,
gpu              1211 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	if (a5xx_crashdumper_init(gpu, &dumper))
gpu              1249 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	if (a5xx_crashdumper_run(gpu, &dumper)) {
gpu              1251 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		msm_gem_kernel_put(dumper.bo, gpu->aspace, true);
gpu              1259 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	msm_gem_kernel_put(dumper.bo, gpu->aspace, true);
gpu              1262 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static struct msm_gpu_state *a5xx_gpu_state_get(struct msm_gpu *gpu)
gpu              1271 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	a5xx_set_hwcg(gpu, false);
gpu              1274 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	adreno_gpu_state_get(gpu, &(a5xx_state->base));
gpu              1276 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	a5xx_state->base.rbbm_status = gpu_read(gpu, REG_A5XX_RBBM_STATUS);
gpu              1279 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	a5xx_gpu_state_get_hlsq_regs(gpu, a5xx_state);
gpu              1281 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	a5xx_set_hwcg(gpu, true);
gpu              1309 drivers/gpu/drm/msm/adreno/a5xx_gpu.c void a5xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
gpu              1320 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	adreno_show(gpu, state, p);
gpu              1350 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static struct msm_ringbuffer *a5xx_active_ring(struct msm_gpu *gpu)
gpu              1352 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu              1358 drivers/gpu/drm/msm/adreno/a5xx_gpu.c static unsigned long a5xx_gpu_busy(struct msm_gpu *gpu)
gpu              1362 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	busy_cycles = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_RBBM_0_LO,
gpu              1365 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	busy_time = busy_cycles - gpu->devfreq.busy_cycles;
gpu              1366 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	do_div(busy_time, clk_get_rate(gpu->core_clk) / 1000000);
gpu              1368 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu->devfreq.busy_cycles = busy_cycles;
gpu              1426 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	struct msm_gpu *gpu;
gpu              1439 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	gpu = &adreno_gpu->base;
gpu              1454 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	if (gpu->aspace)
gpu              1455 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 		msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, a5xx_fault_handler);
gpu              1458 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	a5xx_preempt_init(gpu);
gpu              1460 drivers/gpu/drm/msm/adreno/a5xx_gpu.c 	return gpu;
gpu                44 drivers/gpu/drm/msm/adreno/a5xx_gpu.h int a5xx_debugfs_init(struct msm_gpu *gpu, struct drm_minor *minor);
gpu               127 drivers/gpu/drm/msm/adreno/a5xx_gpu.h int a5xx_power_init(struct msm_gpu *gpu);
gpu               128 drivers/gpu/drm/msm/adreno/a5xx_gpu.h void a5xx_gpmu_ucode_init(struct msm_gpu *gpu);
gpu               130 drivers/gpu/drm/msm/adreno/a5xx_gpu.h static inline int spin_usecs(struct msm_gpu *gpu, uint32_t usecs,
gpu               135 drivers/gpu/drm/msm/adreno/a5xx_gpu.h 		if ((gpu_read(gpu, reg) & mask) == value)
gpu               143 drivers/gpu/drm/msm/adreno/a5xx_gpu.h bool a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
gpu               144 drivers/gpu/drm/msm/adreno/a5xx_gpu.h void a5xx_set_hwcg(struct msm_gpu *gpu, bool state);
gpu               146 drivers/gpu/drm/msm/adreno/a5xx_gpu.h void a5xx_preempt_init(struct msm_gpu *gpu);
gpu               147 drivers/gpu/drm/msm/adreno/a5xx_gpu.h void a5xx_preempt_hw_init(struct msm_gpu *gpu);
gpu               148 drivers/gpu/drm/msm/adreno/a5xx_gpu.h void a5xx_preempt_trigger(struct msm_gpu *gpu);
gpu               149 drivers/gpu/drm/msm/adreno/a5xx_gpu.h void a5xx_preempt_irq(struct msm_gpu *gpu);
gpu               150 drivers/gpu/drm/msm/adreno/a5xx_gpu.h void a5xx_preempt_fini(struct msm_gpu *gpu);
gpu               103 drivers/gpu/drm/msm/adreno/a5xx_power.c static inline uint32_t _get_mvolts(struct msm_gpu *gpu, uint32_t freq)
gpu               105 drivers/gpu/drm/msm/adreno/a5xx_power.c 	struct drm_device *dev = gpu->dev;
gpu               122 drivers/gpu/drm/msm/adreno/a5xx_power.c static void a530_lm_setup(struct msm_gpu *gpu)
gpu               124 drivers/gpu/drm/msm/adreno/a5xx_power.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               130 drivers/gpu/drm/msm/adreno/a5xx_power.c 		gpu_write(gpu, a5xx_sequence_regs[i].reg,
gpu               134 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_ID, 0x60007);
gpu               135 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD, 0x01);
gpu               136 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_CONFIG, 0x01);
gpu               139 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE, 0x80000000 | 0);
gpu               141 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, REG_A5XX_GPMU_BASE_LEAKAGE, a5xx_gpu->lm_leakage);
gpu               144 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, REG_A5XX_GPMU_GPMU_PWR_THRESHOLD, 0x80000000 | 6000);
gpu               146 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, REG_A5XX_GPMU_BEC_ENABLE, 0x10001FFF);
gpu               147 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, REG_A5XX_GDPM_CONFIG1, 0x00201FF1);
gpu               150 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, REG_A5XX_GPMU_BEC_ENABLE, 0x10001FFF);
gpu               151 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, REG_A5XX_GDPM_CONFIG1, 0x201FF1);
gpu               153 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, AGC_MSG_STATE, 1);
gpu               154 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, AGC_MSG_COMMAND, AGC_POWER_CONFIG_PRODUCTION_ID);
gpu               157 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, AGC_MSG_PAYLOAD(0), 5448);
gpu               158 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, AGC_MSG_PAYLOAD(1), 1);
gpu               164 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, AGC_MSG_PAYLOAD(2), _get_mvolts(gpu, gpu->fast_rate));
gpu               165 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, AGC_MSG_PAYLOAD(3), gpu->fast_rate / 1000000);
gpu               167 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, AGC_MSG_PAYLOAD_SIZE, 4 * sizeof(uint32_t));
gpu               168 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, AGC_INIT_MSG_MAGIC, AGC_INIT_MSG_VALUE);
gpu               175 drivers/gpu/drm/msm/adreno/a5xx_power.c static void a540_lm_setup(struct msm_gpu *gpu)
gpu               177 drivers/gpu/drm/msm/adreno/a5xx_power.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               188 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE, 0x80000000 | 0);
gpu               191 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, REG_A5XX_GPMU_GPMU_PWR_THRESHOLD, 0x80000000 | 6000);
gpu               193 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, AGC_MSG_STATE, 0x80000001);
gpu               194 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, AGC_MSG_COMMAND, AGC_POWER_CONFIG_PRODUCTION_ID);
gpu               196 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, AGC_MSG_PAYLOAD(0), 5448);
gpu               197 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, AGC_MSG_PAYLOAD(1), 1);
gpu               199 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, AGC_MSG_PAYLOAD(2), _get_mvolts(gpu, gpu->fast_rate));
gpu               200 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, AGC_MSG_PAYLOAD(3), gpu->fast_rate / 1000000);
gpu               202 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, AGC_MSG_PAYLOAD(AGC_LM_CONFIG), config);
gpu               203 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, AGC_MSG_PAYLOAD(AGC_LEVEL_CONFIG), LEVEL_CONFIG);
gpu               204 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, AGC_MSG_PAYLOAD_SIZE,
gpu               207 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, AGC_INIT_MSG_MAGIC, AGC_INIT_MSG_VALUE);
gpu               211 drivers/gpu/drm/msm/adreno/a5xx_power.c static void a5xx_pc_init(struct msm_gpu *gpu)
gpu               213 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL, 0x7F);
gpu               214 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_BINNING_CTRL, 0);
gpu               215 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST, 0xA0080);
gpu               216 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY, 0x600040);
gpu               220 drivers/gpu/drm/msm/adreno/a5xx_power.c static int a5xx_gpmu_init(struct msm_gpu *gpu)
gpu               222 drivers/gpu/drm/msm/adreno/a5xx_power.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               224 drivers/gpu/drm/msm/adreno/a5xx_power.c 	struct msm_ringbuffer *ring = gpu->rb[0];
gpu               243 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu->funcs->flush(gpu, ring);
gpu               245 drivers/gpu/drm/msm/adreno/a5xx_power.c 	if (!a5xx_idle(gpu, ring)) {
gpu               247 drivers/gpu/drm/msm/adreno/a5xx_power.c 			gpu->name);
gpu               252 drivers/gpu/drm/msm/adreno/a5xx_power.c 		gpu_write(gpu, REG_A5XX_GPMU_WFI_CONFIG, 0x4014);
gpu               255 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, REG_A5XX_GPMU_CM3_SYSRESET, 0x0);
gpu               261 drivers/gpu/drm/msm/adreno/a5xx_power.c 	if (spin_usecs(gpu, 25, REG_A5XX_GPMU_GENERAL_0, 0xFFFFFFFF,
gpu               264 drivers/gpu/drm/msm/adreno/a5xx_power.c 			gpu->name);
gpu               267 drivers/gpu/drm/msm/adreno/a5xx_power.c 		u32 val = gpu_read(gpu, REG_A5XX_GPMU_GENERAL_1);
gpu               271 drivers/gpu/drm/msm/adreno/a5xx_power.c 				  gpu->name, val);
gpu               278 drivers/gpu/drm/msm/adreno/a5xx_power.c static void a5xx_lm_enable(struct msm_gpu *gpu)
gpu               280 drivers/gpu/drm/msm/adreno/a5xx_power.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               286 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, REG_A5XX_GDPM_INT_MASK, 0x0);
gpu               287 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, REG_A5XX_GDPM_INT_EN, 0x0A);
gpu               288 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK, 0x01);
gpu               289 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK, 0x50000);
gpu               290 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL, 0x30000);
gpu               292 drivers/gpu/drm/msm/adreno/a5xx_power.c 	gpu_write(gpu, REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL, 0x011);
gpu               295 drivers/gpu/drm/msm/adreno/a5xx_power.c int a5xx_power_init(struct msm_gpu *gpu)
gpu               297 drivers/gpu/drm/msm/adreno/a5xx_power.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               302 drivers/gpu/drm/msm/adreno/a5xx_power.c 		a530_lm_setup(gpu);
gpu               304 drivers/gpu/drm/msm/adreno/a5xx_power.c 		a540_lm_setup(gpu);
gpu               307 drivers/gpu/drm/msm/adreno/a5xx_power.c 	a5xx_pc_init(gpu);
gpu               310 drivers/gpu/drm/msm/adreno/a5xx_power.c 	ret = a5xx_gpmu_init(gpu);
gpu               315 drivers/gpu/drm/msm/adreno/a5xx_power.c 	a5xx_lm_enable(gpu);
gpu               320 drivers/gpu/drm/msm/adreno/a5xx_power.c void a5xx_gpmu_ucode_init(struct msm_gpu *gpu)
gpu               322 drivers/gpu/drm/msm/adreno/a5xx_power.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               324 drivers/gpu/drm/msm/adreno/a5xx_power.c 	struct drm_device *drm = gpu->dev;
gpu               359 drivers/gpu/drm/msm/adreno/a5xx_power.c 		MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace,
gpu                25 drivers/gpu/drm/msm/adreno/a5xx_preempt.c static inline void set_preempt_state(struct a5xx_gpu *gpu,
gpu                34 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	atomic_set(&gpu->preempt_state, new);
gpu                40 drivers/gpu/drm/msm/adreno/a5xx_preempt.c static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
gpu                52 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr);
gpu                56 drivers/gpu/drm/msm/adreno/a5xx_preempt.c static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu)
gpu                61 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	for (i = 0; i < gpu->nr_rings; i++) {
gpu                63 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 		struct msm_ringbuffer *ring = gpu->rb[i];
gpu                79 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	struct msm_gpu *gpu = &a5xx_gpu->base.base;
gpu                80 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	struct drm_device *dev = gpu->dev;
gpu                86 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	DRM_DEV_ERROR(dev->dev, "%s: preemption timed out\n", gpu->name);
gpu                87 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	queue_work(priv->wq, &gpu->recover_work);
gpu                91 drivers/gpu/drm/msm/adreno/a5xx_preempt.c void a5xx_preempt_trigger(struct msm_gpu *gpu)
gpu                93 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu                98 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	if (gpu->nr_rings == 1)
gpu               109 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	ring = get_next_ring(gpu);
gpu               129 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 		update_wptr(gpu, a5xx_gpu->cur_ring);
gpu               140 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	gpu_write64(gpu, REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO,
gpu               156 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	gpu_write(gpu, REG_A5XX_CP_CONTEXT_SWITCH_CNTL, 1);
gpu               159 drivers/gpu/drm/msm/adreno/a5xx_preempt.c void a5xx_preempt_irq(struct msm_gpu *gpu)
gpu               162 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               164 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	struct drm_device *dev = gpu->dev;
gpu               179 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	status = gpu_read(gpu, REG_A5XX_CP_CONTEXT_SWITCH_CNTL);
gpu               183 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 			gpu->name);
gpu               184 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 		queue_work(priv->wq, &gpu->recover_work);
gpu               191 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	update_wptr(gpu, a5xx_gpu->cur_ring);
gpu               196 drivers/gpu/drm/msm/adreno/a5xx_preempt.c void a5xx_preempt_hw_init(struct msm_gpu *gpu)
gpu               198 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               203 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	a5xx_gpu->cur_ring = gpu->rb[0];
gpu               206 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	if (gpu->nr_rings == 1)
gpu               209 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	for (i = 0; i < gpu->nr_rings; i++) {
gpu               212 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 		a5xx_gpu->preempt[i]->rbase = gpu->rb[i]->iova;
gpu               216 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	gpu_write64(gpu, REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO,
gpu               227 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	struct msm_gpu *gpu = &adreno_gpu->base;
gpu               232 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	ptr = msm_gem_kernel_new(gpu->dev,
gpu               234 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 		MSM_BO_UNCACHED, gpu->aspace, &bo, &iova);
gpu               257 drivers/gpu/drm/msm/adreno/a5xx_preempt.c void a5xx_preempt_fini(struct msm_gpu *gpu)
gpu               259 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               263 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	for (i = 0; i < gpu->nr_rings; i++)
gpu               264 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 		msm_gem_kernel_put(a5xx_gpu->preempt_bo[i], gpu->aspace, true);
gpu               267 drivers/gpu/drm/msm/adreno/a5xx_preempt.c void a5xx_preempt_init(struct msm_gpu *gpu)
gpu               269 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               274 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	if (gpu->nr_rings <= 1)
gpu               277 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 	for (i = 0; i < gpu->nr_rings; i++) {
gpu               278 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 		if (preempt_init_ring(a5xx_gpu, gpu->rb[i])) {
gpu               283 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 			a5xx_preempt_fini(gpu);
gpu               284 drivers/gpu/drm/msm/adreno/a5xx_preempt.c 			gpu->nr_rings = 1;
gpu                17 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	struct msm_gpu *gpu = &adreno_gpu->base;
gpu                18 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	struct drm_device *dev = gpu->dev;
gpu                25 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	del_timer(&gpu->hangcheck_timer);
gpu                28 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	queue_work(priv->wq, &gpu->recover_work);
gpu               107 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	struct msm_gpu *gpu = &adreno_gpu->base;
gpu               135 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216));
gpu               138 drivers/gpu/drm/msm/adreno/a6xx_gmu.c void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq)
gpu               140 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               155 drivers/gpu/drm/msm/adreno/a6xx_gmu.c unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu)
gpu               157 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               696 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	struct msm_gpu *gpu = &adreno_gpu->base;
gpu               717 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	icc_set_bw(gpu->icc_path, 0, MBps_to_icc(3072));
gpu               786 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	struct msm_gpu *gpu = &adreno_gpu->base;
gpu               805 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 		gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf);
gpu               806 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 		spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & 0xf)
gpu               808 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 		gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0);
gpu               846 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	struct msm_gpu *gpu = &a6xx_gpu->base.base;
gpu               861 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	icc_set_bw(gpu->icc_path, 0, 0);
gpu              1095 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	struct msm_gpu *gpu = &adreno_gpu->base;
gpu              1099 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes,
gpu              1145 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	struct msm_gpu *gpu = &adreno_gpu->base;
gpu              1166 drivers/gpu/drm/msm/adreno/a6xx_gmu.c 	gmu->nr_gpu_freqs = a6xx_gmu_build_freq_table(&gpu->pdev->dev,
gpu                15 drivers/gpu/drm/msm/adreno/a6xx_gpu.c static inline bool _a6xx_check_idle(struct msm_gpu *gpu)
gpu                17 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu                25 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) &
gpu                29 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) &
gpu                33 drivers/gpu/drm/msm/adreno/a6xx_gpu.c bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
gpu                36 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	if (!adreno_idle(gpu, ring))
gpu                39 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	if (spin_until(_a6xx_check_idle(gpu))) {
gpu                41 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 			gpu->name, __builtin_return_address(0),
gpu                42 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 			gpu_read(gpu, REG_A6XX_RBBM_STATUS),
gpu                43 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 			gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS),
gpu                44 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 			gpu_read(gpu, REG_A6XX_CP_RB_RPTR),
gpu                45 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 			gpu_read(gpu, REG_A6XX_CP_RB_WPTR));
gpu                52 drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
gpu                70 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr);
gpu                82 drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
gpu                86 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	struct msm_drm_private *priv = gpu->dev->dev_private;
gpu                87 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               151 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	a6xx_flush(gpu, ring);
gpu               265 drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
gpu               267 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               273 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL);
gpu               283 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		gpu_write(gpu, a6xx_hwcg[i].offset,
gpu               289 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? 0x8aa8aa02 : 0);
gpu               292 drivers/gpu/drm/msm/adreno/a6xx_gpu.c static int a6xx_cp_init(struct msm_gpu *gpu)
gpu               294 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	struct msm_ringbuffer *ring = gpu->rb[0];
gpu               317 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	a6xx_flush(gpu, ring);
gpu               318 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	return a6xx_idle(gpu, ring) ? 0 : -EINVAL;
gpu               321 drivers/gpu/drm/msm/adreno/a6xx_gpu.c static int a6xx_ucode_init(struct msm_gpu *gpu)
gpu               323 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               327 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		a6xx_gpu->sqe_bo = adreno_fw_create_bo(gpu,
gpu               334 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 			DRM_DEV_ERROR(&gpu->pdev->dev,
gpu               343 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE_LO,
gpu               349 drivers/gpu/drm/msm/adreno/a6xx_gpu.c static int a6xx_zap_shader_init(struct msm_gpu *gpu)
gpu               357 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	ret = adreno_zap_shader_load(gpu, GPU_PAS_ID);
gpu               375 drivers/gpu/drm/msm/adreno/a6xx_gpu.c static int a6xx_hw_init(struct msm_gpu *gpu)
gpu               377 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               384 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0);
gpu               391 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO,
gpu               393 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000);
gpu               396 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1);
gpu               397 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1);
gpu               398 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1);
gpu               399 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1);
gpu               400 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1);
gpu               401 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1);
gpu               402 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1);
gpu               403 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1);
gpu               404 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1);
gpu               405 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1);
gpu               406 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1);
gpu               407 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);
gpu               410 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	a6xx_set_hwcg(gpu, true);
gpu               413 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009);
gpu               414 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3);
gpu               417 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff);
gpu               420 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_LO, 0xffffffc0);
gpu               421 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_HI, 0x0001ffff);
gpu               422 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_LO, 0xfffff000);
gpu               423 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_HI, 0x0001ffff);
gpu               424 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000);
gpu               425 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff);
gpu               428 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO,
gpu               431 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX_LO,
gpu               435 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804);
gpu               436 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4);
gpu               438 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0);
gpu               439 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c);
gpu               442 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);
gpu               445 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, (0x300 << 11));
gpu               448 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1);
gpu               451 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1);
gpu               454 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT);
gpu               456 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 2 << 1);
gpu               457 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 2 << 1);
gpu               458 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 2 << 1);
gpu               459 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 2 << 21);
gpu               462 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL,
gpu               465 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1);
gpu               468 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, 0x00000003);
gpu               470 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_PROTECT(0),
gpu               472 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_PROTECT(1), A6XX_PROTECT_RW(0xae50, 0x2));
gpu               473 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_PROTECT(2), A6XX_PROTECT_RW(0x9624, 0x13));
gpu               474 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_PROTECT(3), A6XX_PROTECT_RW(0x8630, 0x8));
gpu               475 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_PROTECT(4), A6XX_PROTECT_RW(0x9e70, 0x1));
gpu               476 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_PROTECT(5), A6XX_PROTECT_RW(0x9e78, 0x187));
gpu               477 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_PROTECT(6), A6XX_PROTECT_RW(0xf000, 0x810));
gpu               478 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_PROTECT(7),
gpu               480 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_PROTECT(8), A6XX_PROTECT_RW(0x50e, 0x0));
gpu               481 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_PROTECT(9), A6XX_PROTECT_RDONLY(0x50f, 0x0));
gpu               482 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_PROTECT(10), A6XX_PROTECT_RW(0x510, 0x0));
gpu               483 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_PROTECT(11),
gpu               485 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_PROTECT(12),
gpu               487 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_PROTECT(13),
gpu               489 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_PROTECT(14), A6XX_PROTECT_RW(0xe00, 0xe));
gpu               490 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_PROTECT(15), A6XX_PROTECT_RW(0x8e00, 0x0));
gpu               491 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_PROTECT(16), A6XX_PROTECT_RW(0x8e50, 0xf));
gpu               492 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_PROTECT(17), A6XX_PROTECT_RW(0xbe02, 0x0));
gpu               493 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_PROTECT(18),
gpu               495 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_PROTECT(19), A6XX_PROTECT_RW(0x800, 0x82));
gpu               496 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_PROTECT(20), A6XX_PROTECT_RW(0x8a0, 0x8));
gpu               497 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_PROTECT(21), A6XX_PROTECT_RW(0x8ab, 0x19));
gpu               498 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_PROTECT(22), A6XX_PROTECT_RW(0x900, 0x4d));
gpu               499 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_PROTECT(23), A6XX_PROTECT_RW(0x98d, 0x76));
gpu               500 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_PROTECT(24),
gpu               502 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_PROTECT(25), A6XX_PROTECT_RW(0xa630, 0x0));
gpu               505 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_INT_MASK);
gpu               507 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	ret = adreno_hw_init(gpu);
gpu               511 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	ret = a6xx_ucode_init(gpu);
gpu               516 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	a6xx_gpu->cur_ring = gpu->rb[0];
gpu               519 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1);
gpu               521 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	ret = a6xx_cp_init(gpu);
gpu               532 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	ret = a6xx_zap_shader_init(gpu);
gpu               534 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1);
gpu               535 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		OUT_RING(gpu->rb[0], 0x00000000);
gpu               537 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		a6xx_flush(gpu, gpu->rb[0]);
gpu               538 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		if (!a6xx_idle(gpu, gpu->rb[0]))
gpu               547 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		dev_warn_once(gpu->dev->dev,
gpu               549 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0);
gpu               568 drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_dump(struct msm_gpu *gpu)
gpu               570 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	DRM_DEV_INFO(&gpu->pdev->dev, "status:   %08x\n",
gpu               571 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 			gpu_read(gpu, REG_A6XX_RBBM_STATUS));
gpu               572 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	adreno_dump(gpu);
gpu               578 drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_recover(struct msm_gpu *gpu)
gpu               580 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               584 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	adreno_dump_info(gpu);
gpu               587 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i,
gpu               588 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i)));
gpu               591 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		a6xx_dump(gpu);
gpu               599 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu->funcs->pm_suspend(gpu);
gpu               600 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu->funcs->pm_resume(gpu);
gpu               602 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	msm_gpu_hw_init(gpu);
gpu               607 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	struct msm_gpu *gpu = arg;
gpu               611 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),
gpu               612 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),
gpu               613 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),
gpu               614 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 			gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)));
gpu               619 drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu)
gpu               621 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS);
gpu               626 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		gpu_write(gpu, REG_A6XX_CP_SQE_STAT_ADDR, 1);
gpu               627 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA);
gpu               628 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		dev_err_ratelimited(&gpu->pdev->dev,
gpu               634 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		dev_err_ratelimited(&gpu->pdev->dev,
gpu               638 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		dev_err_ratelimited(&gpu->pdev->dev, "CP | HW fault | status=0x%8.8X\n",
gpu               639 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 			gpu_read(gpu, REG_A6XX_CP_HW_FAULT));
gpu               642 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS);
gpu               644 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		dev_err_ratelimited(&gpu->pdev->dev,
gpu               651 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		dev_err_ratelimited(&gpu->pdev->dev, "CP AHB error interrupt\n");
gpu               654 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		dev_err_ratelimited(&gpu->pdev->dev, "CP VSD decoder parity error\n");
gpu               657 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		dev_err_ratelimited(&gpu->pdev->dev, "CP illegal instruction error\n");
gpu               661 drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
gpu               663 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               665 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	struct drm_device *dev = gpu->dev;
gpu               667 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
gpu               675 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	DRM_DEV_ERROR(&gpu->pdev->dev,
gpu               678 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		gpu_read(gpu, REG_A6XX_RBBM_STATUS),
gpu               679 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		gpu_read(gpu, REG_A6XX_CP_RB_RPTR),
gpu               680 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		gpu_read(gpu, REG_A6XX_CP_RB_WPTR),
gpu               681 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		gpu_read64(gpu, REG_A6XX_CP_IB1_BASE, REG_A6XX_CP_IB1_BASE_HI),
gpu               682 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE),
gpu               683 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		gpu_read64(gpu, REG_A6XX_CP_IB2_BASE, REG_A6XX_CP_IB2_BASE_HI),
gpu               684 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE));
gpu               687 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	del_timer(&gpu->hangcheck_timer);
gpu               689 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	queue_work(priv->wq, &gpu->recover_work);
gpu               692 drivers/gpu/drm/msm/adreno/a6xx_gpu.c static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
gpu               694 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS);
gpu               696 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status);
gpu               699 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		a6xx_fault_detect_irq(gpu);
gpu               702 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n");
gpu               705 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		a6xx_cp_hw_err_irq(gpu);
gpu               708 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n");
gpu               711 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n");
gpu               714 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n");
gpu               717 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		msm_gpu_retire(gpu);
gpu               734 drivers/gpu/drm/msm/adreno/a6xx_gpu.c static int a6xx_pm_resume(struct msm_gpu *gpu)
gpu               736 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               740 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu->needs_hw_init = true;
gpu               746 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	msm_gpu_resume_devfreq(gpu);
gpu               751 drivers/gpu/drm/msm/adreno/a6xx_gpu.c static int a6xx_pm_suspend(struct msm_gpu *gpu)
gpu               753 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               756 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	devfreq_suspend_device(gpu->devfreq.devfreq);
gpu               761 drivers/gpu/drm/msm/adreno/a6xx_gpu.c static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
gpu               763 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               769 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	*value = gpu_read64(gpu, REG_A6XX_RBBM_PERFCTR_CP_0_LO,
gpu               776 drivers/gpu/drm/msm/adreno/a6xx_gpu.c static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu)
gpu               778 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               784 drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_destroy(struct msm_gpu *gpu)
gpu               786 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               790 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace);
gpu               800 drivers/gpu/drm/msm/adreno/a6xx_gpu.c static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu)
gpu               802 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               810 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	busy_time = (busy_cycles - gpu->devfreq.busy_cycles) * 10;
gpu               813 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu->devfreq.busy_cycles = busy_cycles;
gpu               854 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	struct msm_gpu *gpu;
gpu               862 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	gpu = &adreno_gpu->base;
gpu               885 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	if (gpu->aspace)
gpu               886 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 		msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu,
gpu               889 drivers/gpu/drm/msm/adreno/a6xx_gpu.c 	return gpu;
gpu                46 drivers/gpu/drm/msm/adreno/a6xx_gpu.h int a6xx_gmu_resume(struct a6xx_gpu *gpu);
gpu                47 drivers/gpu/drm/msm/adreno/a6xx_gpu.h int a6xx_gmu_stop(struct a6xx_gpu *gpu);
gpu                59 drivers/gpu/drm/msm/adreno/a6xx_gpu.h void a6xx_gmu_set_freq(struct msm_gpu *gpu, unsigned long freq);
gpu                60 drivers/gpu/drm/msm/adreno/a6xx_gpu.h unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu);
gpu                62 drivers/gpu/drm/msm/adreno/a6xx_gpu.h void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
gpu                65 drivers/gpu/drm/msm/adreno/a6xx_gpu.h struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu);
gpu               112 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c static int a6xx_crashdumper_init(struct msm_gpu *gpu,
gpu               115 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	dumper->ptr = msm_gem_kernel_new_locked(gpu->dev,
gpu               116 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 		SZ_1M, MSM_BO_UNCACHED, gpu->aspace,
gpu               125 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c static int a6xx_crashdumper_run(struct msm_gpu *gpu,
gpu               128 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               142 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write64(gpu, REG_A6XX_CP_CRASH_SCRIPT_BASE_LO,
gpu               145 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 1);
gpu               147 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	ret = gpu_poll_timeout(gpu, REG_A6XX_CP_CRASH_DUMP_STATUS, val,
gpu               150 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 0);
gpu               156 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c static int debugbus_read(struct msm_gpu *gpu, u32 block, u32 offset,
gpu               162 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_A, reg);
gpu               163 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_B, reg);
gpu               164 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_C, reg);
gpu               165 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_D, reg);
gpu               170 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	data[0] = gpu_read(gpu, REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2);
gpu               171 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	data[1] = gpu_read(gpu, REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1);
gpu               204 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c static int vbif_debugbus_read(struct msm_gpu *gpu, u32 ctrl0, u32 ctrl1,
gpu               209 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write(gpu, ctrl0, reg);
gpu               212 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 		gpu_write(gpu, ctrl1, i);
gpu               213 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 		data[i] = gpu_read(gpu, REG_A6XX_VBIF_TEST_BUS_OUT);
gpu               228 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c static void a6xx_get_vbif_debugbus_block(struct msm_gpu *gpu,
gpu               243 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	clk = gpu_read(gpu, REG_A6XX_VBIF_CLKON);
gpu               246 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write(gpu, REG_A6XX_VBIF_CLKON,
gpu               250 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write(gpu, REG_A6XX_VBIF_TEST_BUS1_CTRL0, 0);
gpu               253 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write(gpu, REG_A6XX_VBIF_TEST_BUS_OUT_CTRL, 1);
gpu               258 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 		ptr += vbif_debugbus_read(gpu,
gpu               264 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 		ptr += vbif_debugbus_read(gpu,
gpu               270 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write(gpu, REG_A6XX_VBIF_TEST_BUS2_CTRL0, 0);
gpu               273 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 		ptr += vbif_debugbus_read(gpu,
gpu               279 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write(gpu, REG_A6XX_VBIF_CLKON, clk);
gpu               282 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c static void a6xx_get_debugbus_block(struct msm_gpu *gpu,
gpu               297 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 		ptr += debugbus_read(gpu, block->id, i, ptr);
gpu               318 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c static void a6xx_get_debugbus(struct msm_gpu *gpu,
gpu               326 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_CNTLT,
gpu               329 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_CNTLM,
gpu               332 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0, 0);
gpu               333 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1, 0);
gpu               334 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2, 0);
gpu               335 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3, 0);
gpu               337 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0, 0x76543210);
gpu               338 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1, 0xFEDCBA98);
gpu               340 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0, 0);
gpu               341 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1, 0);
gpu               342 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2, 0);
gpu               343 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3, 0);
gpu               348 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	res = platform_get_resource_byname(gpu->pdev, IORESOURCE_MEM,
gpu               385 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 			a6xx_get_debugbus_block(gpu,
gpu               398 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 		a6xx_get_vbif_debugbus_block(gpu, a6xx_state,
gpu               427 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c static void a6xx_get_dbgahb_cluster(struct msm_gpu *gpu,
gpu               465 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	if (a6xx_crashdumper_run(gpu, dumper))
gpu               473 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c static void a6xx_get_dbgahb_clusters(struct msm_gpu *gpu,
gpu               489 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 		a6xx_get_dbgahb_cluster(gpu, a6xx_state,
gpu               495 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c static void a6xx_get_cluster(struct msm_gpu *gpu,
gpu               536 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	if (a6xx_crashdumper_run(gpu, dumper))
gpu               544 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c static void a6xx_get_clusters(struct msm_gpu *gpu,
gpu               559 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 		a6xx_get_cluster(gpu, a6xx_state, &a6xx_clusters[i],
gpu               564 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c static void a6xx_get_shader_block(struct msm_gpu *gpu,
gpu               587 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	if (a6xx_crashdumper_run(gpu, dumper))
gpu               595 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c static void a6xx_get_shaders(struct msm_gpu *gpu,
gpu               610 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 		a6xx_get_shader_block(gpu, a6xx_state, &a6xx_shader_blocks[i],
gpu               615 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c static void a6xx_get_crashdumper_hlsq_registers(struct msm_gpu *gpu,
gpu               644 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	if (a6xx_crashdumper_run(gpu, dumper))
gpu               653 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c static void a6xx_get_crashdumper_registers(struct msm_gpu *gpu,
gpu               682 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	if (a6xx_crashdumper_run(gpu, dumper))
gpu               691 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c static void a6xx_get_ahb_gpu_registers(struct msm_gpu *gpu,
gpu               711 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 			obj->data[index++] = gpu_read(gpu,
gpu               717 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c static void _a6xx_get_gmu_registers(struct msm_gpu *gpu,
gpu               722 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               745 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c static void a6xx_get_gmu_registers(struct msm_gpu *gpu,
gpu               748 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               760 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	_a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[0],
gpu               767 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write(gpu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
gpu               769 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	_a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[1],
gpu               773 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c static void a6xx_get_registers(struct msm_gpu *gpu,
gpu               791 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 		a6xx_get_ahb_gpu_registers(gpu,
gpu               796 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 		a6xx_get_crashdumper_registers(gpu,
gpu               802 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 		a6xx_get_crashdumper_hlsq_registers(gpu,
gpu               809 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c static void a6xx_get_indexed_regs(struct msm_gpu *gpu,
gpu               822 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write(gpu, indexed->addr, 0);
gpu               826 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 		obj->data[i] = gpu_read(gpu, indexed->data);
gpu               829 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c static void a6xx_get_indexed_registers(struct msm_gpu *gpu,
gpu               842 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 		a6xx_get_indexed_regs(gpu, a6xx_state, &a6xx_indexed_reglist[i],
gpu               846 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	mempool_size = gpu_read(gpu, REG_A6XX_CP_MEM_POOL_SIZE);
gpu               847 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 0);
gpu               850 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	a6xx_get_indexed_regs(gpu, a6xx_state, &a6xx_cp_mempool_indexed,
gpu               860 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, mempool_size);
gpu               865 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu)
gpu               868 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               879 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	adreno_gpu_state_get(gpu, &a6xx_state->base);
gpu               881 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	a6xx_get_gmu_registers(gpu, a6xx_state);
gpu               888 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	a6xx_get_indexed_registers(gpu, a6xx_state);
gpu               891 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	if (!a6xx_crashdumper_init(gpu, &dumper)) {
gpu               892 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 		a6xx_get_registers(gpu, a6xx_state, &dumper);
gpu               893 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 		a6xx_get_shaders(gpu, a6xx_state, &dumper);
gpu               894 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 		a6xx_get_clusters(gpu, a6xx_state, &dumper);
gpu               895 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 		a6xx_get_dbgahb_clusters(gpu, a6xx_state, &dumper);
gpu               897 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 		msm_gem_kernel_put(dumper.bo, gpu->aspace, true);
gpu               900 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	a6xx_get_debugbus(gpu, a6xx_state);
gpu              1114 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
gpu              1124 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	adreno_show(gpu, state, p);
gpu               212 drivers/gpu/drm/msm/adreno/adreno_device.c 	struct msm_gpu *gpu = NULL;
gpu               217 drivers/gpu/drm/msm/adreno/adreno_device.c 		gpu = platform_get_drvdata(pdev);
gpu               219 drivers/gpu/drm/msm/adreno/adreno_device.c 	if (!gpu) {
gpu               224 drivers/gpu/drm/msm/adreno/adreno_device.c 	adreno_gpu = to_adreno_gpu(gpu);
gpu               247 drivers/gpu/drm/msm/adreno/adreno_device.c 	ret = msm_gpu_hw_init(gpu);
gpu               256 drivers/gpu/drm/msm/adreno/adreno_device.c 	if (gpu->funcs->debugfs_init) {
gpu               257 drivers/gpu/drm/msm/adreno/adreno_device.c 		gpu->funcs->debugfs_init(gpu, dev->primary);
gpu               258 drivers/gpu/drm/msm/adreno/adreno_device.c 		gpu->funcs->debugfs_init(gpu, dev->render);
gpu               262 drivers/gpu/drm/msm/adreno/adreno_device.c 	return gpu;
gpu               322 drivers/gpu/drm/msm/adreno/adreno_device.c 	struct msm_gpu *gpu;
gpu               346 drivers/gpu/drm/msm/adreno/adreno_device.c 	gpu = info->init(drm);
gpu               347 drivers/gpu/drm/msm/adreno/adreno_device.c 	if (IS_ERR(gpu)) {
gpu               349 drivers/gpu/drm/msm/adreno/adreno_device.c 		return PTR_ERR(gpu);
gpu               352 drivers/gpu/drm/msm/adreno/adreno_device.c 	dev_set_drvdata(dev, gpu);
gpu               360 drivers/gpu/drm/msm/adreno/adreno_device.c 	struct msm_gpu *gpu = dev_get_drvdata(dev);
gpu               363 drivers/gpu/drm/msm/adreno/adreno_device.c 	gpu->funcs->destroy(gpu);
gpu               426 drivers/gpu/drm/msm/adreno/adreno_device.c 	struct msm_gpu *gpu = platform_get_drvdata(pdev);
gpu               428 drivers/gpu/drm/msm/adreno/adreno_device.c 	return gpu->funcs->pm_resume(gpu);
gpu               434 drivers/gpu/drm/msm/adreno/adreno_device.c 	struct msm_gpu *gpu = platform_get_drvdata(pdev);
gpu               436 drivers/gpu/drm/msm/adreno/adreno_device.c 	return gpu->funcs->pm_suspend(gpu);
gpu                23 drivers/gpu/drm/msm/adreno/adreno_gpu.c static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname,
gpu                26 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	struct device *dev = &gpu->pdev->dev;
gpu                61 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	fw = adreno_request_fw(to_adreno_gpu(gpu), fwname);
gpu                97 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	if (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY) {
gpu               133 drivers/gpu/drm/msm/adreno/adreno_gpu.c int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid)
gpu               135 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               136 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	struct platform_device *pdev = gpu->pdev;
gpu               156 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid);
gpu               159 drivers/gpu/drm/msm/adreno/adreno_gpu.c int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)
gpu               161 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               186 drivers/gpu/drm/msm/adreno/adreno_gpu.c 			pm_runtime_get_sync(&gpu->pdev->dev);
gpu               187 drivers/gpu/drm/msm/adreno/adreno_gpu.c 			ret = adreno_gpu->funcs->get_timestamp(gpu, value);
gpu               188 drivers/gpu/drm/msm/adreno/adreno_gpu.c 			pm_runtime_put_autosuspend(&gpu->pdev->dev);
gpu               194 drivers/gpu/drm/msm/adreno/adreno_gpu.c 		*value = gpu->nr_rings;
gpu               200 drivers/gpu/drm/msm/adreno/adreno_gpu.c 		*value = gpu->global_faults;
gpu               203 drivers/gpu/drm/msm/adreno/adreno_gpu.c 		DBG("%s: invalid param: %u", gpu->name, param);
gpu               313 drivers/gpu/drm/msm/adreno/adreno_gpu.c struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
gpu               319 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	ptr = msm_gem_kernel_new_locked(gpu->dev, fw->size - 4,
gpu               320 drivers/gpu/drm/msm/adreno/adreno_gpu.c 		MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova);
gpu               332 drivers/gpu/drm/msm/adreno/adreno_gpu.c int adreno_hw_init(struct msm_gpu *gpu)
gpu               334 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               337 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	DBG("%s", gpu->name);
gpu               343 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	for (i = 0; i < gpu->nr_rings; i++) {
gpu               344 drivers/gpu/drm/msm/adreno/adreno_gpu.c 		struct msm_ringbuffer *ring = gpu->rb[i];
gpu               369 drivers/gpu/drm/msm/adreno/adreno_gpu.c 		REG_ADRENO_CP_RB_BASE_HI, gpu->rb[0]->iova);
gpu               374 drivers/gpu/drm/msm/adreno/adreno_gpu.c 			rbmemptr(gpu->rb[0], rptr));
gpu               391 drivers/gpu/drm/msm/adreno/adreno_gpu.c struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu)
gpu               393 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	return gpu->rb[0];
gpu               396 drivers/gpu/drm/msm/adreno/adreno_gpu.c void adreno_recover(struct msm_gpu *gpu)
gpu               398 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	struct drm_device *dev = gpu->dev;
gpu               404 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	gpu->funcs->pm_suspend(gpu);
gpu               405 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	gpu->funcs->pm_resume(gpu);
gpu               407 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	ret = msm_gpu_hw_init(gpu);
gpu               414 drivers/gpu/drm/msm/adreno/adreno_gpu.c void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
gpu               417 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               418 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	struct msm_drm_private *priv = gpu->dev->dev_private;
gpu               483 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	gpu->funcs->flush(gpu, ring);
gpu               486 drivers/gpu/drm/msm/adreno/adreno_gpu.c void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
gpu               488 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               507 drivers/gpu/drm/msm/adreno/adreno_gpu.c bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
gpu               509 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               518 drivers/gpu/drm/msm/adreno/adreno_gpu.c 		gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr);
gpu               523 drivers/gpu/drm/msm/adreno/adreno_gpu.c int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state)
gpu               525 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               532 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	for (i = 0; i < gpu->nr_rings; i++) {
gpu               535 drivers/gpu/drm/msm/adreno/adreno_gpu.c 		state->ring[i].fence = gpu->rb[i]->memptrs->fence;
gpu               536 drivers/gpu/drm/msm/adreno/adreno_gpu.c 		state->ring[i].iova = gpu->rb[i]->iova;
gpu               537 drivers/gpu/drm/msm/adreno/adreno_gpu.c 		state->ring[i].seqno = gpu->rb[i]->seqno;
gpu               538 drivers/gpu/drm/msm/adreno/adreno_gpu.c 		state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]);
gpu               539 drivers/gpu/drm/msm/adreno/adreno_gpu.c 		state->ring[i].wptr = get_wptr(gpu->rb[i]);
gpu               546 drivers/gpu/drm/msm/adreno/adreno_gpu.c 			if (gpu->rb[i]->start[j])
gpu               552 drivers/gpu/drm/msm/adreno/adreno_gpu.c 				memcpy(state->ring[i].data, gpu->rb[i]->start, size << 2);
gpu               578 drivers/gpu/drm/msm/adreno/adreno_gpu.c 				state->registers[pos++] = gpu_read(gpu, addr);
gpu               695 drivers/gpu/drm/msm/adreno/adreno_gpu.c void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
gpu               698 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               713 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	for (i = 0; i < gpu->nr_rings; i++) {
gpu               757 drivers/gpu/drm/msm/adreno/adreno_gpu.c void adreno_dump_info(struct msm_gpu *gpu)
gpu               759 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               767 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	for (i = 0; i < gpu->nr_rings; i++) {
gpu               768 drivers/gpu/drm/msm/adreno/adreno_gpu.c 		struct msm_ringbuffer *ring = gpu->rb[i];
gpu               780 drivers/gpu/drm/msm/adreno/adreno_gpu.c void adreno_dump(struct msm_gpu *gpu)
gpu               782 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
gpu               789 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	printk("IO:region %s 00000000 00020000\n", gpu->name);
gpu               796 drivers/gpu/drm/msm/adreno/adreno_gpu.c 			uint32_t val = gpu_read(gpu, addr);
gpu               804 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(ring->gpu);
gpu               815 drivers/gpu/drm/msm/adreno/adreno_gpu.c 		DRM_DEV_ERROR(ring->gpu->dev->dev,
gpu               853 drivers/gpu/drm/msm/adreno/adreno_gpu.c 		struct msm_gpu *gpu)
gpu               859 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	gpu->fast_rate = 0;
gpu               874 drivers/gpu/drm/msm/adreno/adreno_gpu.c 			gpu->fast_rate = freq;
gpu               879 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	if (!gpu->fast_rate) {
gpu               883 drivers/gpu/drm/msm/adreno/adreno_gpu.c 		gpu->fast_rate = 200000000;
gpu               886 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate);
gpu               889 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	gpu->icc_path = of_icc_get(dev, NULL);
gpu               890 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	if (IS_ERR(gpu->icc_path))
gpu               891 drivers/gpu/drm/msm/adreno/adreno_gpu.c 		gpu->icc_path = NULL;
gpu               902 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	struct msm_gpu *gpu = &adreno_gpu->base;
gpu               920 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	adreno_get_pwrlevels(&pdev->dev, gpu);
gpu               933 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	struct msm_gpu *gpu = &adreno_gpu->base;
gpu               939 drivers/gpu/drm/msm/adreno/adreno_gpu.c 	icc_put(gpu->icc_path);
gpu                68 drivers/gpu/drm/msm/adreno/adreno_gpu.h 	int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
gpu               148 drivers/gpu/drm/msm/adreno/adreno_gpu.h static inline bool adreno_is_a2xx(struct adreno_gpu *gpu)
gpu               150 drivers/gpu/drm/msm/adreno/adreno_gpu.h 	return (gpu->revn < 300);
gpu               153 drivers/gpu/drm/msm/adreno/adreno_gpu.h static inline bool adreno_is_a20x(struct adreno_gpu *gpu)
gpu               155 drivers/gpu/drm/msm/adreno/adreno_gpu.h 	return (gpu->revn < 210);
gpu               158 drivers/gpu/drm/msm/adreno/adreno_gpu.h static inline bool adreno_is_a225(struct adreno_gpu *gpu)
gpu               160 drivers/gpu/drm/msm/adreno/adreno_gpu.h 	return gpu->revn == 225;
gpu               163 drivers/gpu/drm/msm/adreno/adreno_gpu.h static inline bool adreno_is_a3xx(struct adreno_gpu *gpu)
gpu               165 drivers/gpu/drm/msm/adreno/adreno_gpu.h 	return (gpu->revn >= 300) && (gpu->revn < 400);
gpu               168 drivers/gpu/drm/msm/adreno/adreno_gpu.h static inline bool adreno_is_a305(struct adreno_gpu *gpu)
gpu               170 drivers/gpu/drm/msm/adreno/adreno_gpu.h 	return gpu->revn == 305;
gpu               173 drivers/gpu/drm/msm/adreno/adreno_gpu.h static inline bool adreno_is_a306(struct adreno_gpu *gpu)
gpu               176 drivers/gpu/drm/msm/adreno/adreno_gpu.h 	return gpu->revn == 307;
gpu               179 drivers/gpu/drm/msm/adreno/adreno_gpu.h static inline bool adreno_is_a320(struct adreno_gpu *gpu)
gpu               181 drivers/gpu/drm/msm/adreno/adreno_gpu.h 	return gpu->revn == 320;
gpu               184 drivers/gpu/drm/msm/adreno/adreno_gpu.h static inline bool adreno_is_a330(struct adreno_gpu *gpu)
gpu               186 drivers/gpu/drm/msm/adreno/adreno_gpu.h 	return gpu->revn == 330;
gpu               189 drivers/gpu/drm/msm/adreno/adreno_gpu.h static inline bool adreno_is_a330v2(struct adreno_gpu *gpu)
gpu               191 drivers/gpu/drm/msm/adreno/adreno_gpu.h 	return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
gpu               194 drivers/gpu/drm/msm/adreno/adreno_gpu.h static inline bool adreno_is_a4xx(struct adreno_gpu *gpu)
gpu               196 drivers/gpu/drm/msm/adreno/adreno_gpu.h 	return (gpu->revn >= 400) && (gpu->revn < 500);
gpu               199 drivers/gpu/drm/msm/adreno/adreno_gpu.h static inline int adreno_is_a420(struct adreno_gpu *gpu)
gpu               201 drivers/gpu/drm/msm/adreno/adreno_gpu.h 	return gpu->revn == 420;
gpu               204 drivers/gpu/drm/msm/adreno/adreno_gpu.h static inline int adreno_is_a430(struct adreno_gpu *gpu)
gpu               206 drivers/gpu/drm/msm/adreno/adreno_gpu.h        return gpu->revn == 430;
gpu               209 drivers/gpu/drm/msm/adreno/adreno_gpu.h static inline int adreno_is_a530(struct adreno_gpu *gpu)
gpu               211 drivers/gpu/drm/msm/adreno/adreno_gpu.h 	return gpu->revn == 530;
gpu               214 drivers/gpu/drm/msm/adreno/adreno_gpu.h static inline int adreno_is_a540(struct adreno_gpu *gpu)
gpu               216 drivers/gpu/drm/msm/adreno/adreno_gpu.h 	return gpu->revn == 540;
gpu               219 drivers/gpu/drm/msm/adreno/adreno_gpu.h int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
gpu               222 drivers/gpu/drm/msm/adreno/adreno_gpu.h struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
gpu               224 drivers/gpu/drm/msm/adreno/adreno_gpu.h int adreno_hw_init(struct msm_gpu *gpu);
gpu               225 drivers/gpu/drm/msm/adreno/adreno_gpu.h void adreno_recover(struct msm_gpu *gpu);
gpu               226 drivers/gpu/drm/msm/adreno/adreno_gpu.h void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
gpu               228 drivers/gpu/drm/msm/adreno/adreno_gpu.h void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
gpu               229 drivers/gpu/drm/msm/adreno/adreno_gpu.h bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
gpu               231 drivers/gpu/drm/msm/adreno/adreno_gpu.h void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
gpu               234 drivers/gpu/drm/msm/adreno/adreno_gpu.h void adreno_dump_info(struct msm_gpu *gpu);
gpu               235 drivers/gpu/drm/msm/adreno/adreno_gpu.h void adreno_dump(struct msm_gpu *gpu);
gpu               237 drivers/gpu/drm/msm/adreno/adreno_gpu.h struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu);
gpu               240 drivers/gpu/drm/msm/adreno/adreno_gpu.h 		struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
gpu               242 drivers/gpu/drm/msm/adreno/adreno_gpu.h void adreno_gpu_cleanup(struct adreno_gpu *gpu);
gpu               247 drivers/gpu/drm/msm/adreno/adreno_gpu.h int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
gpu               254 drivers/gpu/drm/msm/adreno/adreno_gpu.h int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid);
gpu               315 drivers/gpu/drm/msm/adreno/adreno_gpu.h static inline bool adreno_reg_check(struct adreno_gpu *gpu,
gpu               319 drivers/gpu/drm/msm/adreno/adreno_gpu.h 			!gpu->reg_offsets[offset_name]) {
gpu               329 drivers/gpu/drm/msm/adreno/adreno_gpu.h 	if (gpu->reg_offsets[offset_name] == REG_SKIP)
gpu               335 drivers/gpu/drm/msm/adreno/adreno_gpu.h static inline u32 adreno_gpu_read(struct adreno_gpu *gpu,
gpu               338 drivers/gpu/drm/msm/adreno/adreno_gpu.h 	u32 reg = gpu->reg_offsets[offset_name];
gpu               340 drivers/gpu/drm/msm/adreno/adreno_gpu.h 	if(adreno_reg_check(gpu,offset_name))
gpu               341 drivers/gpu/drm/msm/adreno/adreno_gpu.h 		val = gpu_read(&gpu->base, reg - 1);
gpu               345 drivers/gpu/drm/msm/adreno/adreno_gpu.h static inline void adreno_gpu_write(struct adreno_gpu *gpu,
gpu               348 drivers/gpu/drm/msm/adreno/adreno_gpu.h 	u32 reg = gpu->reg_offsets[offset_name];
gpu               349 drivers/gpu/drm/msm/adreno/adreno_gpu.h 	if(adreno_reg_check(gpu, offset_name))
gpu               350 drivers/gpu/drm/msm/adreno/adreno_gpu.h 		gpu_write(&gpu->base, reg - 1, data);
gpu               359 drivers/gpu/drm/msm/adreno/adreno_gpu.h static inline void adreno_gpu_write64(struct adreno_gpu *gpu,
gpu               362 drivers/gpu/drm/msm/adreno/adreno_gpu.h 	adreno_gpu_write(gpu, lo, lower_32_bits(data));
gpu               363 drivers/gpu/drm/msm/adreno/adreno_gpu.h 	adreno_gpu_write(gpu, hi, upper_32_bits(data));
gpu               396 drivers/gpu/drm/msm/adreno/adreno_gpu.h #define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \
gpu               397 drivers/gpu/drm/msm/adreno/adreno_gpu.h 	readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \
gpu               109 drivers/gpu/drm/msm/msm_atomic_trace.h #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/msm
gpu                29 drivers/gpu/drm/msm/msm_debugfs.c 	struct msm_gpu *gpu = priv->gpu;
gpu                36 drivers/gpu/drm/msm/msm_debugfs.c 	drm_printf(&p, "%s Status:\n", gpu->name);
gpu                37 drivers/gpu/drm/msm/msm_debugfs.c 	gpu->funcs->show(gpu, show_priv->state, &p);
gpu                49 drivers/gpu/drm/msm/msm_debugfs.c 	struct msm_gpu *gpu = priv->gpu;
gpu                52 drivers/gpu/drm/msm/msm_debugfs.c 	gpu->funcs->gpu_state_put(show_priv->state);
gpu                64 drivers/gpu/drm/msm/msm_debugfs.c 	struct msm_gpu *gpu = priv->gpu;
gpu                68 drivers/gpu/drm/msm/msm_debugfs.c 	if (!gpu || !gpu->funcs->gpu_state_get)
gpu                79 drivers/gpu/drm/msm/msm_debugfs.c 	pm_runtime_get_sync(&gpu->pdev->dev);
gpu                80 drivers/gpu/drm/msm/msm_debugfs.c 	show_priv->state = gpu->funcs->gpu_state_get(gpu);
gpu                81 drivers/gpu/drm/msm/msm_debugfs.c 	pm_runtime_put_sync(&gpu->pdev->dev);
gpu               114 drivers/gpu/drm/msm/msm_debugfs.c 	struct msm_gpu *gpu = priv->gpu;
gpu               116 drivers/gpu/drm/msm/msm_debugfs.c 	if (gpu) {
gpu               117 drivers/gpu/drm/msm/msm_debugfs.c 		seq_printf(m, "Active Objects (%s):\n", gpu->name);
gpu               118 drivers/gpu/drm/msm/msm_debugfs.c 		msm_gem_describe_objects(&gpu->active_list, m);
gpu               582 drivers/gpu/drm/msm/msm_drv.c 	if (!priv->gpu)
gpu               583 drivers/gpu/drm/msm/msm_drv.c 		priv->gpu = adreno_load_gpu(dev);
gpu               599 drivers/gpu/drm/msm/msm_drv.c 	ctx->aspace = priv->gpu ? priv->gpu->aspace : NULL;
gpu               700 drivers/gpu/drm/msm/msm_drv.c 	struct msm_gpu *gpu;
gpu               708 drivers/gpu/drm/msm/msm_drv.c 	gpu = priv->gpu;
gpu               710 drivers/gpu/drm/msm/msm_drv.c 	if (!gpu)
gpu               713 drivers/gpu/drm/msm/msm_drv.c 	return gpu->funcs->get_param(gpu, args->param, &args->value);
gpu               782 drivers/gpu/drm/msm/msm_drv.c 	if (!priv->gpu)
gpu               789 drivers/gpu/drm/msm/msm_drv.c 	return msm_gem_get_iova(obj, priv->gpu->aspace, iova);
gpu               876 drivers/gpu/drm/msm/msm_drv.c 	struct msm_gpu *gpu = priv->gpu;
gpu               884 drivers/gpu/drm/msm/msm_drv.c 	if (!gpu)
gpu               891 drivers/gpu/drm/msm/msm_drv.c 	ret = msm_wait_fence(gpu->rb[queue->prio]->fctx, args->fence, &timeout,
gpu               163 drivers/gpu/drm/msm/msm_drv.h 	struct msm_gpu *gpu;
gpu               254 drivers/gpu/drm/msm/msm_drv.h msm_gem_address_space_create_a2xx(struct device *dev, struct msm_gpu *gpu,
gpu               303 drivers/gpu/drm/msm/msm_drv.h 		struct msm_gpu *gpu, bool exclusive, struct dma_fence *fence);
gpu               737 drivers/gpu/drm/msm/msm_gem.c 		struct msm_gpu *gpu, bool exclusive, struct dma_fence *fence)
gpu               741 drivers/gpu/drm/msm/msm_gem.c 	msm_obj->gpu = gpu;
gpu               747 drivers/gpu/drm/msm/msm_gem.c 	list_add_tail(&msm_obj->mm_list, &gpu->active_list);
gpu               758 drivers/gpu/drm/msm/msm_gem.c 	msm_obj->gpu = NULL;
gpu                61 drivers/gpu/drm/msm/msm_gem.h 	struct msm_gpu *gpu;     /* non-null if active */
gpu                90 drivers/gpu/drm/msm/msm_gem.h 	return msm_obj->gpu != NULL;
gpu               132 drivers/gpu/drm/msm/msm_gem.h 	struct msm_gpu *gpu;
gpu                28 drivers/gpu/drm/msm/msm_gem_submit.c 		struct msm_gpu *gpu, struct msm_gem_address_space *aspace,
gpu                45 drivers/gpu/drm/msm/msm_gem_submit.c 	submit->gpu = gpu;
gpu                49 drivers/gpu/drm/msm/msm_gem_submit.c 	submit->ring = gpu->rb[queue->prio];
gpu               405 drivers/gpu/drm/msm/msm_gem_submit.c 	struct msm_gpu *gpu = priv->gpu;
gpu               413 drivers/gpu/drm/msm/msm_gem_submit.c 	if (!gpu)
gpu               438 drivers/gpu/drm/msm/msm_gem_submit.c 	ring = gpu->rb[queue->prio];
gpu               475 drivers/gpu/drm/msm/msm_gem_submit.c 	submit = submit_create(dev, gpu, ctx->aspace, queue, args->nr_bos,
gpu               580 drivers/gpu/drm/msm/msm_gem_submit.c 	msm_gpu_submit(gpu, submit, ctx);
gpu               154 drivers/gpu/drm/msm/msm_gem_vma.c msm_gem_address_space_create_a2xx(struct device *dev, struct msm_gpu *gpu,
gpu               166 drivers/gpu/drm/msm/msm_gem_vma.c 	aspace->mmu = msm_gpummu_new(dev, gpu);
gpu                28 drivers/gpu/drm/msm/msm_gpu.c 	struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
gpu                36 drivers/gpu/drm/msm/msm_gpu.c 	if (gpu->funcs->gpu_set_freq)
gpu                37 drivers/gpu/drm/msm/msm_gpu.c 		gpu->funcs->gpu_set_freq(gpu, (u64)*freq);
gpu                39 drivers/gpu/drm/msm/msm_gpu.c 		clk_set_rate(gpu->core_clk, *freq);
gpu                49 drivers/gpu/drm/msm/msm_gpu.c 	struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
gpu                52 drivers/gpu/drm/msm/msm_gpu.c 	if (gpu->funcs->gpu_get_freq)
gpu                53 drivers/gpu/drm/msm/msm_gpu.c 		status->current_frequency = gpu->funcs->gpu_get_freq(gpu);
gpu                55 drivers/gpu/drm/msm/msm_gpu.c 		status->current_frequency = clk_get_rate(gpu->core_clk);
gpu                57 drivers/gpu/drm/msm/msm_gpu.c 	status->busy_time = gpu->funcs->gpu_busy(gpu);
gpu                60 drivers/gpu/drm/msm/msm_gpu.c 	status->total_time = ktime_us_delta(time, gpu->devfreq.time);
gpu                61 drivers/gpu/drm/msm/msm_gpu.c 	gpu->devfreq.time = time;
gpu                68 drivers/gpu/drm/msm/msm_gpu.c 	struct msm_gpu *gpu = platform_get_drvdata(to_platform_device(dev));
gpu                70 drivers/gpu/drm/msm/msm_gpu.c 	if (gpu->funcs->gpu_get_freq)
gpu                71 drivers/gpu/drm/msm/msm_gpu.c 		*freq = gpu->funcs->gpu_get_freq(gpu);
gpu                73 drivers/gpu/drm/msm/msm_gpu.c 		*freq = clk_get_rate(gpu->core_clk);
gpu                85 drivers/gpu/drm/msm/msm_gpu.c static void msm_devfreq_init(struct msm_gpu *gpu)
gpu                88 drivers/gpu/drm/msm/msm_gpu.c 	if (!gpu->funcs->gpu_busy)
gpu                91 drivers/gpu/drm/msm/msm_gpu.c 	msm_devfreq_profile.initial_freq = gpu->fast_rate;
gpu                98 drivers/gpu/drm/msm/msm_gpu.c 	gpu->devfreq.devfreq = devm_devfreq_add_device(&gpu->pdev->dev,
gpu               102 drivers/gpu/drm/msm/msm_gpu.c 	if (IS_ERR(gpu->devfreq.devfreq)) {
gpu               103 drivers/gpu/drm/msm/msm_gpu.c 		DRM_DEV_ERROR(&gpu->pdev->dev, "Couldn't initialize GPU devfreq\n");
gpu               104 drivers/gpu/drm/msm/msm_gpu.c 		gpu->devfreq.devfreq = NULL;
gpu               107 drivers/gpu/drm/msm/msm_gpu.c 	devfreq_suspend_device(gpu->devfreq.devfreq);
gpu               110 drivers/gpu/drm/msm/msm_gpu.c static int enable_pwrrail(struct msm_gpu *gpu)
gpu               112 drivers/gpu/drm/msm/msm_gpu.c 	struct drm_device *dev = gpu->dev;
gpu               115 drivers/gpu/drm/msm/msm_gpu.c 	if (gpu->gpu_reg) {
gpu               116 drivers/gpu/drm/msm/msm_gpu.c 		ret = regulator_enable(gpu->gpu_reg);
gpu               123 drivers/gpu/drm/msm/msm_gpu.c 	if (gpu->gpu_cx) {
gpu               124 drivers/gpu/drm/msm/msm_gpu.c 		ret = regulator_enable(gpu->gpu_cx);
gpu               134 drivers/gpu/drm/msm/msm_gpu.c static int disable_pwrrail(struct msm_gpu *gpu)
gpu               136 drivers/gpu/drm/msm/msm_gpu.c 	if (gpu->gpu_cx)
gpu               137 drivers/gpu/drm/msm/msm_gpu.c 		regulator_disable(gpu->gpu_cx);
gpu               138 drivers/gpu/drm/msm/msm_gpu.c 	if (gpu->gpu_reg)
gpu               139 drivers/gpu/drm/msm/msm_gpu.c 		regulator_disable(gpu->gpu_reg);
gpu               143 drivers/gpu/drm/msm/msm_gpu.c static int enable_clk(struct msm_gpu *gpu)
gpu               145 drivers/gpu/drm/msm/msm_gpu.c 	if (gpu->core_clk && gpu->fast_rate)
gpu               146 drivers/gpu/drm/msm/msm_gpu.c 		clk_set_rate(gpu->core_clk, gpu->fast_rate);
gpu               149 drivers/gpu/drm/msm/msm_gpu.c 	if (gpu->rbbmtimer_clk)
gpu               150 drivers/gpu/drm/msm/msm_gpu.c 		clk_set_rate(gpu->rbbmtimer_clk, 19200000);
gpu               152 drivers/gpu/drm/msm/msm_gpu.c 	return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks);
gpu               155 drivers/gpu/drm/msm/msm_gpu.c static int disable_clk(struct msm_gpu *gpu)
gpu               157 drivers/gpu/drm/msm/msm_gpu.c 	clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks);
gpu               164 drivers/gpu/drm/msm/msm_gpu.c 	if (gpu->core_clk)
gpu               165 drivers/gpu/drm/msm/msm_gpu.c 		clk_set_rate(gpu->core_clk, 27000000);
gpu               167 drivers/gpu/drm/msm/msm_gpu.c 	if (gpu->rbbmtimer_clk)
gpu               168 drivers/gpu/drm/msm/msm_gpu.c 		clk_set_rate(gpu->rbbmtimer_clk, 0);
gpu               173 drivers/gpu/drm/msm/msm_gpu.c static int enable_axi(struct msm_gpu *gpu)
gpu               175 drivers/gpu/drm/msm/msm_gpu.c 	if (gpu->ebi1_clk)
gpu               176 drivers/gpu/drm/msm/msm_gpu.c 		clk_prepare_enable(gpu->ebi1_clk);
gpu               180 drivers/gpu/drm/msm/msm_gpu.c static int disable_axi(struct msm_gpu *gpu)
gpu               182 drivers/gpu/drm/msm/msm_gpu.c 	if (gpu->ebi1_clk)
gpu               183 drivers/gpu/drm/msm/msm_gpu.c 		clk_disable_unprepare(gpu->ebi1_clk);
gpu               187 drivers/gpu/drm/msm/msm_gpu.c void msm_gpu_resume_devfreq(struct msm_gpu *gpu)
gpu               189 drivers/gpu/drm/msm/msm_gpu.c 	gpu->devfreq.busy_cycles = 0;
gpu               190 drivers/gpu/drm/msm/msm_gpu.c 	gpu->devfreq.time = ktime_get();
gpu               192 drivers/gpu/drm/msm/msm_gpu.c 	devfreq_resume_device(gpu->devfreq.devfreq);
gpu               195 drivers/gpu/drm/msm/msm_gpu.c int msm_gpu_pm_resume(struct msm_gpu *gpu)
gpu               199 drivers/gpu/drm/msm/msm_gpu.c 	DBG("%s", gpu->name);
gpu               201 drivers/gpu/drm/msm/msm_gpu.c 	ret = enable_pwrrail(gpu);
gpu               205 drivers/gpu/drm/msm/msm_gpu.c 	ret = enable_clk(gpu);
gpu               209 drivers/gpu/drm/msm/msm_gpu.c 	ret = enable_axi(gpu);
gpu               213 drivers/gpu/drm/msm/msm_gpu.c 	msm_gpu_resume_devfreq(gpu);
gpu               215 drivers/gpu/drm/msm/msm_gpu.c 	gpu->needs_hw_init = true;
gpu               220 drivers/gpu/drm/msm/msm_gpu.c int msm_gpu_pm_suspend(struct msm_gpu *gpu)
gpu               224 drivers/gpu/drm/msm/msm_gpu.c 	DBG("%s", gpu->name);
gpu               226 drivers/gpu/drm/msm/msm_gpu.c 	devfreq_suspend_device(gpu->devfreq.devfreq);
gpu               228 drivers/gpu/drm/msm/msm_gpu.c 	ret = disable_axi(gpu);
gpu               232 drivers/gpu/drm/msm/msm_gpu.c 	ret = disable_clk(gpu);
gpu               236 drivers/gpu/drm/msm/msm_gpu.c 	ret = disable_pwrrail(gpu);
gpu               243 drivers/gpu/drm/msm/msm_gpu.c int msm_gpu_hw_init(struct msm_gpu *gpu)
gpu               247 drivers/gpu/drm/msm/msm_gpu.c 	WARN_ON(!mutex_is_locked(&gpu->dev->struct_mutex));
gpu               249 drivers/gpu/drm/msm/msm_gpu.c 	if (!gpu->needs_hw_init)
gpu               252 drivers/gpu/drm/msm/msm_gpu.c 	disable_irq(gpu->irq);
gpu               253 drivers/gpu/drm/msm/msm_gpu.c 	ret = gpu->funcs->hw_init(gpu);
gpu               255 drivers/gpu/drm/msm/msm_gpu.c 		gpu->needs_hw_init = false;
gpu               256 drivers/gpu/drm/msm/msm_gpu.c 	enable_irq(gpu->irq);
gpu               265 drivers/gpu/drm/msm/msm_gpu.c 	struct msm_gpu *gpu = data;
gpu               270 drivers/gpu/drm/msm/msm_gpu.c 	state = msm_gpu_crashstate_get(gpu);
gpu               291 drivers/gpu/drm/msm/msm_gpu.c 	gpu->funcs->show(gpu, state, &p);
gpu               293 drivers/gpu/drm/msm/msm_gpu.c 	msm_gpu_crashstate_put(gpu);
gpu               300 drivers/gpu/drm/msm/msm_gpu.c 	struct msm_gpu *gpu = data;
gpu               302 drivers/gpu/drm/msm/msm_gpu.c 	msm_gpu_crashstate_put(gpu);
gpu               336 drivers/gpu/drm/msm/msm_gpu.c static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
gpu               342 drivers/gpu/drm/msm/msm_gpu.c 	if (!gpu->funcs->gpu_state_get)
gpu               346 drivers/gpu/drm/msm/msm_gpu.c 	if (gpu->crashstate)
gpu               349 drivers/gpu/drm/msm/msm_gpu.c 	state = gpu->funcs->gpu_state_get(gpu);
gpu               372 drivers/gpu/drm/msm/msm_gpu.c 	gpu->crashstate = state;
gpu               375 drivers/gpu/drm/msm/msm_gpu.c 	dev_coredumpm(gpu->dev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL,
gpu               379 drivers/gpu/drm/msm/msm_gpu.c static void msm_gpu_crashstate_capture(struct msm_gpu *gpu,
gpu               389 drivers/gpu/drm/msm/msm_gpu.c static void update_fences(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
gpu               408 drivers/gpu/drm/msm/msm_gpu.c 	WARN_ON(!mutex_is_locked(&ring->gpu->dev->struct_mutex));
gpu               417 drivers/gpu/drm/msm/msm_gpu.c static void retire_submits(struct msm_gpu *gpu);
gpu               421 drivers/gpu/drm/msm/msm_gpu.c 	struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work);
gpu               422 drivers/gpu/drm/msm/msm_gpu.c 	struct drm_device *dev = gpu->dev;
gpu               425 drivers/gpu/drm/msm/msm_gpu.c 	struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu);
gpu               431 drivers/gpu/drm/msm/msm_gpu.c 	DRM_DEV_ERROR(dev->dev, "%s: hangcheck recover!\n", gpu->name);
gpu               438 drivers/gpu/drm/msm/msm_gpu.c 		gpu->global_faults++;
gpu               450 drivers/gpu/drm/msm/msm_gpu.c 				gpu->name, comm, cmd);
gpu               459 drivers/gpu/drm/msm/msm_gpu.c 	pm_runtime_get_sync(&gpu->pdev->dev);
gpu               460 drivers/gpu/drm/msm/msm_gpu.c 	msm_gpu_crashstate_capture(gpu, submit, comm, cmd);
gpu               461 drivers/gpu/drm/msm/msm_gpu.c 	pm_runtime_put_sync(&gpu->pdev->dev);
gpu               471 drivers/gpu/drm/msm/msm_gpu.c 	for (i = 0; i < gpu->nr_rings; i++) {
gpu               472 drivers/gpu/drm/msm/msm_gpu.c 		struct msm_ringbuffer *ring = gpu->rb[i];
gpu               483 drivers/gpu/drm/msm/msm_gpu.c 		update_fences(gpu, ring, fence);
gpu               486 drivers/gpu/drm/msm/msm_gpu.c 	if (msm_gpu_active(gpu)) {
gpu               488 drivers/gpu/drm/msm/msm_gpu.c 		retire_submits(gpu);
gpu               490 drivers/gpu/drm/msm/msm_gpu.c 		pm_runtime_get_sync(&gpu->pdev->dev);
gpu               491 drivers/gpu/drm/msm/msm_gpu.c 		gpu->funcs->recover(gpu);
gpu               492 drivers/gpu/drm/msm/msm_gpu.c 		pm_runtime_put_sync(&gpu->pdev->dev);
gpu               498 drivers/gpu/drm/msm/msm_gpu.c 		for (i = 0; i < gpu->nr_rings; i++) {
gpu               499 drivers/gpu/drm/msm/msm_gpu.c 			struct msm_ringbuffer *ring = gpu->rb[i];
gpu               502 drivers/gpu/drm/msm/msm_gpu.c 				gpu->funcs->submit(gpu, submit, NULL);
gpu               508 drivers/gpu/drm/msm/msm_gpu.c 	msm_gpu_retire(gpu);
gpu               511 drivers/gpu/drm/msm/msm_gpu.c static void hangcheck_timer_reset(struct msm_gpu *gpu)
gpu               513 drivers/gpu/drm/msm/msm_gpu.c 	DBG("%s", gpu->name);
gpu               514 drivers/gpu/drm/msm/msm_gpu.c 	mod_timer(&gpu->hangcheck_timer,
gpu               520 drivers/gpu/drm/msm/msm_gpu.c 	struct msm_gpu *gpu = from_timer(gpu, t, hangcheck_timer);
gpu               521 drivers/gpu/drm/msm/msm_gpu.c 	struct drm_device *dev = gpu->dev;
gpu               523 drivers/gpu/drm/msm/msm_gpu.c 	struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
gpu               533 drivers/gpu/drm/msm/msm_gpu.c 				gpu->name, ring->id);
gpu               535 drivers/gpu/drm/msm/msm_gpu.c 				gpu->name, fence);
gpu               537 drivers/gpu/drm/msm/msm_gpu.c 				gpu->name, ring->seqno);
gpu               539 drivers/gpu/drm/msm/msm_gpu.c 		queue_work(priv->wq, &gpu->recover_work);
gpu               544 drivers/gpu/drm/msm/msm_gpu.c 		hangcheck_timer_reset(gpu);
gpu               547 drivers/gpu/drm/msm/msm_gpu.c 	queue_work(priv->wq, &gpu->retire_work);
gpu               555 drivers/gpu/drm/msm/msm_gpu.c static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs)
gpu               557 drivers/gpu/drm/msm/msm_gpu.c 	uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)];
gpu               558 drivers/gpu/drm/msm/msm_gpu.c 	int i, n = min(ncntrs, gpu->num_perfcntrs);
gpu               561 drivers/gpu/drm/msm/msm_gpu.c 	for (i = 0; i < gpu->num_perfcntrs; i++)
gpu               562 drivers/gpu/drm/msm/msm_gpu.c 		current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg);
gpu               566 drivers/gpu/drm/msm/msm_gpu.c 		cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i];
gpu               569 drivers/gpu/drm/msm/msm_gpu.c 	for (i = 0; i < gpu->num_perfcntrs; i++)
gpu               570 drivers/gpu/drm/msm/msm_gpu.c 		gpu->last_cntrs[i] = current_cntrs[i];
gpu               575 drivers/gpu/drm/msm/msm_gpu.c static void update_sw_cntrs(struct msm_gpu *gpu)
gpu               581 drivers/gpu/drm/msm/msm_gpu.c 	spin_lock_irqsave(&gpu->perf_lock, flags);
gpu               582 drivers/gpu/drm/msm/msm_gpu.c 	if (!gpu->perfcntr_active)
gpu               586 drivers/gpu/drm/msm/msm_gpu.c 	elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time));
gpu               588 drivers/gpu/drm/msm/msm_gpu.c 	gpu->totaltime += elapsed;
gpu               589 drivers/gpu/drm/msm/msm_gpu.c 	if (gpu->last_sample.active)
gpu               590 drivers/gpu/drm/msm/msm_gpu.c 		gpu->activetime += elapsed;
gpu               592 drivers/gpu/drm/msm/msm_gpu.c 	gpu->last_sample.active = msm_gpu_active(gpu);
gpu               593 drivers/gpu/drm/msm/msm_gpu.c 	gpu->last_sample.time = time;
gpu               596 drivers/gpu/drm/msm/msm_gpu.c 	spin_unlock_irqrestore(&gpu->perf_lock, flags);
gpu               599 drivers/gpu/drm/msm/msm_gpu.c void msm_gpu_perfcntr_start(struct msm_gpu *gpu)
gpu               603 drivers/gpu/drm/msm/msm_gpu.c 	pm_runtime_get_sync(&gpu->pdev->dev);
gpu               605 drivers/gpu/drm/msm/msm_gpu.c 	spin_lock_irqsave(&gpu->perf_lock, flags);
gpu               607 drivers/gpu/drm/msm/msm_gpu.c 	gpu->last_sample.active = msm_gpu_active(gpu);
gpu               608 drivers/gpu/drm/msm/msm_gpu.c 	gpu->last_sample.time = ktime_get();
gpu               609 drivers/gpu/drm/msm/msm_gpu.c 	gpu->activetime = gpu->totaltime = 0;
gpu               610 drivers/gpu/drm/msm/msm_gpu.c 	gpu->perfcntr_active = true;
gpu               611 drivers/gpu/drm/msm/msm_gpu.c 	update_hw_cntrs(gpu, 0, NULL);
gpu               612 drivers/gpu/drm/msm/msm_gpu.c 	spin_unlock_irqrestore(&gpu->perf_lock, flags);
gpu               615 drivers/gpu/drm/msm/msm_gpu.c void msm_gpu_perfcntr_stop(struct msm_gpu *gpu)
gpu               617 drivers/gpu/drm/msm/msm_gpu.c 	gpu->perfcntr_active = false;
gpu               618 drivers/gpu/drm/msm/msm_gpu.c 	pm_runtime_put_sync(&gpu->pdev->dev);
gpu               622 drivers/gpu/drm/msm/msm_gpu.c int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
gpu               628 drivers/gpu/drm/msm/msm_gpu.c 	spin_lock_irqsave(&gpu->perf_lock, flags);
gpu               630 drivers/gpu/drm/msm/msm_gpu.c 	if (!gpu->perfcntr_active) {
gpu               635 drivers/gpu/drm/msm/msm_gpu.c 	*activetime = gpu->activetime;
gpu               636 drivers/gpu/drm/msm/msm_gpu.c 	*totaltime = gpu->totaltime;
gpu               638 drivers/gpu/drm/msm/msm_gpu.c 	gpu->activetime = gpu->totaltime = 0;
gpu               640 drivers/gpu/drm/msm/msm_gpu.c 	ret = update_hw_cntrs(gpu, ncntrs, cntrs);
gpu               643 drivers/gpu/drm/msm/msm_gpu.c 	spin_unlock_irqrestore(&gpu->perf_lock, flags);
gpu               652 drivers/gpu/drm/msm/msm_gpu.c static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
gpu               682 drivers/gpu/drm/msm/msm_gpu.c 	pm_runtime_mark_last_busy(&gpu->pdev->dev);
gpu               683 drivers/gpu/drm/msm/msm_gpu.c 	pm_runtime_put_autosuspend(&gpu->pdev->dev);
gpu               687 drivers/gpu/drm/msm/msm_gpu.c static void retire_submits(struct msm_gpu *gpu)
gpu               689 drivers/gpu/drm/msm/msm_gpu.c 	struct drm_device *dev = gpu->dev;
gpu               696 drivers/gpu/drm/msm/msm_gpu.c 	for (i = 0; i < gpu->nr_rings; i++) {
gpu               697 drivers/gpu/drm/msm/msm_gpu.c 		struct msm_ringbuffer *ring = gpu->rb[i];
gpu               701 drivers/gpu/drm/msm/msm_gpu.c 				retire_submit(gpu, ring, submit);
gpu               708 drivers/gpu/drm/msm/msm_gpu.c 	struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work);
gpu               709 drivers/gpu/drm/msm/msm_gpu.c 	struct drm_device *dev = gpu->dev;
gpu               712 drivers/gpu/drm/msm/msm_gpu.c 	for (i = 0; i < gpu->nr_rings; i++)
gpu               713 drivers/gpu/drm/msm/msm_gpu.c 		update_fences(gpu, gpu->rb[i], gpu->rb[i]->memptrs->fence);
gpu               716 drivers/gpu/drm/msm/msm_gpu.c 	retire_submits(gpu);
gpu               721 drivers/gpu/drm/msm/msm_gpu.c void msm_gpu_retire(struct msm_gpu *gpu)
gpu               723 drivers/gpu/drm/msm/msm_gpu.c 	struct msm_drm_private *priv = gpu->dev->dev_private;
gpu               724 drivers/gpu/drm/msm/msm_gpu.c 	queue_work(priv->wq, &gpu->retire_work);
gpu               725 drivers/gpu/drm/msm/msm_gpu.c 	update_sw_cntrs(gpu);
gpu               729 drivers/gpu/drm/msm/msm_gpu.c void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
gpu               732 drivers/gpu/drm/msm/msm_gpu.c 	struct drm_device *dev = gpu->dev;
gpu               739 drivers/gpu/drm/msm/msm_gpu.c 	pm_runtime_get_sync(&gpu->pdev->dev);
gpu               741 drivers/gpu/drm/msm/msm_gpu.c 	msm_gpu_hw_init(gpu);
gpu               749 drivers/gpu/drm/msm/msm_gpu.c 	update_sw_cntrs(gpu);
gpu               758 drivers/gpu/drm/msm/msm_gpu.c 		WARN_ON(is_active(msm_obj) && (msm_obj->gpu != gpu));
gpu               765 drivers/gpu/drm/msm/msm_gpu.c 			msm_gem_move_to_active(&msm_obj->base, gpu, true, submit->fence);
gpu               767 drivers/gpu/drm/msm/msm_gpu.c 			msm_gem_move_to_active(&msm_obj->base, gpu, false, submit->fence);
gpu               770 drivers/gpu/drm/msm/msm_gpu.c 	gpu->funcs->submit(gpu, submit, ctx);
gpu               773 drivers/gpu/drm/msm/msm_gpu.c 	hangcheck_timer_reset(gpu);
gpu               782 drivers/gpu/drm/msm/msm_gpu.c 	struct msm_gpu *gpu = data;
gpu               783 drivers/gpu/drm/msm/msm_gpu.c 	return gpu->funcs->irq(gpu);
gpu               786 drivers/gpu/drm/msm/msm_gpu.c static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu)
gpu               788 drivers/gpu/drm/msm/msm_gpu.c 	int ret = devm_clk_bulk_get_all(&pdev->dev, &gpu->grp_clks);
gpu               791 drivers/gpu/drm/msm/msm_gpu.c 		gpu->nr_clocks = 0;
gpu               795 drivers/gpu/drm/msm/msm_gpu.c 	gpu->nr_clocks = ret;
gpu               797 drivers/gpu/drm/msm/msm_gpu.c 	gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
gpu               798 drivers/gpu/drm/msm/msm_gpu.c 		gpu->nr_clocks, "core");
gpu               800 drivers/gpu/drm/msm/msm_gpu.c 	gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks,
gpu               801 drivers/gpu/drm/msm/msm_gpu.c 		gpu->nr_clocks, "rbbmtimer");
gpu               807 drivers/gpu/drm/msm/msm_gpu.c msm_gpu_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev,
gpu               818 drivers/gpu/drm/msm/msm_gpu.c 	if (!adreno_is_a2xx(to_adreno_gpu(gpu))) {
gpu               826 drivers/gpu/drm/msm/msm_gpu.c 		DRM_DEV_INFO(gpu->dev->dev, "%s: using IOMMU\n", gpu->name);
gpu               832 drivers/gpu/drm/msm/msm_gpu.c 		aspace = msm_gem_address_space_create_a2xx(&pdev->dev, gpu, "gpu",
gpu               837 drivers/gpu/drm/msm/msm_gpu.c 		DRM_DEV_ERROR(gpu->dev->dev, "failed to init mmu: %ld\n",
gpu               852 drivers/gpu/drm/msm/msm_gpu.c 		struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
gpu               859 drivers/gpu/drm/msm/msm_gpu.c 	if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs)))
gpu               860 drivers/gpu/drm/msm/msm_gpu.c 		gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs);
gpu               862 drivers/gpu/drm/msm/msm_gpu.c 	gpu->dev = drm;
gpu               863 drivers/gpu/drm/msm/msm_gpu.c 	gpu->funcs = funcs;
gpu               864 drivers/gpu/drm/msm/msm_gpu.c 	gpu->name = name;
gpu               866 drivers/gpu/drm/msm/msm_gpu.c 	INIT_LIST_HEAD(&gpu->active_list);
gpu               867 drivers/gpu/drm/msm/msm_gpu.c 	INIT_WORK(&gpu->retire_work, retire_worker);
gpu               868 drivers/gpu/drm/msm/msm_gpu.c 	INIT_WORK(&gpu->recover_work, recover_worker);
gpu               871 drivers/gpu/drm/msm/msm_gpu.c 	timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0);
gpu               873 drivers/gpu/drm/msm/msm_gpu.c 	spin_lock_init(&gpu->perf_lock);
gpu               877 drivers/gpu/drm/msm/msm_gpu.c 	gpu->mmio = msm_ioremap(pdev, config->ioname, name);
gpu               878 drivers/gpu/drm/msm/msm_gpu.c 	if (IS_ERR(gpu->mmio)) {
gpu               879 drivers/gpu/drm/msm/msm_gpu.c 		ret = PTR_ERR(gpu->mmio);
gpu               884 drivers/gpu/drm/msm/msm_gpu.c 	gpu->irq = platform_get_irq(pdev, 0);
gpu               885 drivers/gpu/drm/msm/msm_gpu.c 	if (gpu->irq < 0) {
gpu               886 drivers/gpu/drm/msm/msm_gpu.c 		ret = gpu->irq;
gpu               891 drivers/gpu/drm/msm/msm_gpu.c 	ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler,
gpu               892 drivers/gpu/drm/msm/msm_gpu.c 			IRQF_TRIGGER_HIGH, gpu->name, gpu);
gpu               894 drivers/gpu/drm/msm/msm_gpu.c 		DRM_DEV_ERROR(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret);
gpu               898 drivers/gpu/drm/msm/msm_gpu.c 	ret = get_clocks(pdev, gpu);
gpu               902 drivers/gpu/drm/msm/msm_gpu.c 	gpu->ebi1_clk = msm_clk_get(pdev, "bus");
gpu               903 drivers/gpu/drm/msm/msm_gpu.c 	DBG("ebi1_clk: %p", gpu->ebi1_clk);
gpu               904 drivers/gpu/drm/msm/msm_gpu.c 	if (IS_ERR(gpu->ebi1_clk))
gpu               905 drivers/gpu/drm/msm/msm_gpu.c 		gpu->ebi1_clk = NULL;
gpu               908 drivers/gpu/drm/msm/msm_gpu.c 	gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd");
gpu               909 drivers/gpu/drm/msm/msm_gpu.c 	DBG("gpu_reg: %p", gpu->gpu_reg);
gpu               910 drivers/gpu/drm/msm/msm_gpu.c 	if (IS_ERR(gpu->gpu_reg))
gpu               911 drivers/gpu/drm/msm/msm_gpu.c 		gpu->gpu_reg = NULL;
gpu               913 drivers/gpu/drm/msm/msm_gpu.c 	gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx");
gpu               914 drivers/gpu/drm/msm/msm_gpu.c 	DBG("gpu_cx: %p", gpu->gpu_cx);
gpu               915 drivers/gpu/drm/msm/msm_gpu.c 	if (IS_ERR(gpu->gpu_cx))
gpu               916 drivers/gpu/drm/msm/msm_gpu.c 		gpu->gpu_cx = NULL;
gpu               918 drivers/gpu/drm/msm/msm_gpu.c 	gpu->pdev = pdev;
gpu               919 drivers/gpu/drm/msm/msm_gpu.c 	platform_set_drvdata(pdev, gpu);
gpu               921 drivers/gpu/drm/msm/msm_gpu.c 	msm_devfreq_init(gpu);
gpu               923 drivers/gpu/drm/msm/msm_gpu.c 	gpu->aspace = msm_gpu_create_address_space(gpu, pdev,
gpu               926 drivers/gpu/drm/msm/msm_gpu.c 	if (gpu->aspace == NULL)
gpu               928 drivers/gpu/drm/msm/msm_gpu.c 	else if (IS_ERR(gpu->aspace)) {
gpu               929 drivers/gpu/drm/msm/msm_gpu.c 		ret = PTR_ERR(gpu->aspace);
gpu               935 drivers/gpu/drm/msm/msm_gpu.c 		MSM_BO_UNCACHED, gpu->aspace, &gpu->memptrs_bo,
gpu               944 drivers/gpu/drm/msm/msm_gpu.c 	msm_gem_object_set_name(gpu->memptrs_bo, "memptrs");
gpu               946 drivers/gpu/drm/msm/msm_gpu.c 	if (nr_rings > ARRAY_SIZE(gpu->rb)) {
gpu               948 drivers/gpu/drm/msm/msm_gpu.c 			ARRAY_SIZE(gpu->rb));
gpu               949 drivers/gpu/drm/msm/msm_gpu.c 		nr_rings = ARRAY_SIZE(gpu->rb);
gpu               954 drivers/gpu/drm/msm/msm_gpu.c 		gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova);
gpu               956 drivers/gpu/drm/msm/msm_gpu.c 		if (IS_ERR(gpu->rb[i])) {
gpu               957 drivers/gpu/drm/msm/msm_gpu.c 			ret = PTR_ERR(gpu->rb[i]);
gpu               967 drivers/gpu/drm/msm/msm_gpu.c 	gpu->nr_rings = nr_rings;
gpu               972 drivers/gpu/drm/msm/msm_gpu.c 	for (i = 0; i < ARRAY_SIZE(gpu->rb); i++)  {
gpu               973 drivers/gpu/drm/msm/msm_gpu.c 		msm_ringbuffer_destroy(gpu->rb[i]);
gpu               974 drivers/gpu/drm/msm/msm_gpu.c 		gpu->rb[i] = NULL;
gpu               977 drivers/gpu/drm/msm/msm_gpu.c 	msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace, false);
gpu               983 drivers/gpu/drm/msm/msm_gpu.c void msm_gpu_cleanup(struct msm_gpu *gpu)
gpu               987 drivers/gpu/drm/msm/msm_gpu.c 	DBG("%s", gpu->name);
gpu               989 drivers/gpu/drm/msm/msm_gpu.c 	WARN_ON(!list_empty(&gpu->active_list));
gpu               991 drivers/gpu/drm/msm/msm_gpu.c 	for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) {
gpu               992 drivers/gpu/drm/msm/msm_gpu.c 		msm_ringbuffer_destroy(gpu->rb[i]);
gpu               993 drivers/gpu/drm/msm/msm_gpu.c 		gpu->rb[i] = NULL;
gpu               996 drivers/gpu/drm/msm/msm_gpu.c 	msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace, false);
gpu               998 drivers/gpu/drm/msm/msm_gpu.c 	if (!IS_ERR_OR_NULL(gpu->aspace)) {
gpu               999 drivers/gpu/drm/msm/msm_gpu.c 		gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu,
gpu              1001 drivers/gpu/drm/msm/msm_gpu.c 		msm_gem_address_space_put(gpu->aspace);
gpu                44 drivers/gpu/drm/msm/msm_gpu.h 	int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
gpu                45 drivers/gpu/drm/msm/msm_gpu.h 	int (*hw_init)(struct msm_gpu *gpu);
gpu                46 drivers/gpu/drm/msm/msm_gpu.h 	int (*pm_suspend)(struct msm_gpu *gpu);
gpu                47 drivers/gpu/drm/msm/msm_gpu.h 	int (*pm_resume)(struct msm_gpu *gpu);
gpu                48 drivers/gpu/drm/msm/msm_gpu.h 	void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit,
gpu                50 drivers/gpu/drm/msm/msm_gpu.h 	void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
gpu                52 drivers/gpu/drm/msm/msm_gpu.h 	struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
gpu                53 drivers/gpu/drm/msm/msm_gpu.h 	void (*recover)(struct msm_gpu *gpu);
gpu                54 drivers/gpu/drm/msm/msm_gpu.h 	void (*destroy)(struct msm_gpu *gpu);
gpu                57 drivers/gpu/drm/msm/msm_gpu.h 	void (*show)(struct msm_gpu *gpu, struct msm_gpu_state *state,
gpu                60 drivers/gpu/drm/msm/msm_gpu.h 	int (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor);
gpu                62 drivers/gpu/drm/msm/msm_gpu.h 	unsigned long (*gpu_busy)(struct msm_gpu *gpu);
gpu                63 drivers/gpu/drm/msm/msm_gpu.h 	struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu);
gpu                65 drivers/gpu/drm/msm/msm_gpu.h 	unsigned long (*gpu_get_freq)(struct msm_gpu *gpu);
gpu                66 drivers/gpu/drm/msm/msm_gpu.h 	void (*gpu_set_freq)(struct msm_gpu *gpu, unsigned long freq);
gpu               144 drivers/gpu/drm/msm/msm_gpu.h static inline bool msm_gpu_active(struct msm_gpu *gpu)
gpu               148 drivers/gpu/drm/msm/msm_gpu.h 	for (i = 0; i < gpu->nr_rings; i++) {
gpu               149 drivers/gpu/drm/msm/msm_gpu.h 		struct msm_ringbuffer *ring = gpu->rb[i];
gpu               214 drivers/gpu/drm/msm/msm_gpu.h static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
gpu               216 drivers/gpu/drm/msm/msm_gpu.h 	msm_writel(data, gpu->mmio + (reg << 2));
gpu               219 drivers/gpu/drm/msm/msm_gpu.h static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
gpu               221 drivers/gpu/drm/msm/msm_gpu.h 	return msm_readl(gpu->mmio + (reg << 2));
gpu               224 drivers/gpu/drm/msm/msm_gpu.h static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)
gpu               226 drivers/gpu/drm/msm/msm_gpu.h 	uint32_t val = gpu_read(gpu, reg);
gpu               229 drivers/gpu/drm/msm/msm_gpu.h 	gpu_write(gpu, reg, val | or);
gpu               232 drivers/gpu/drm/msm/msm_gpu.h static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi)
gpu               250 drivers/gpu/drm/msm/msm_gpu.h 	val = (u64) msm_readl(gpu->mmio + (lo << 2));
gpu               251 drivers/gpu/drm/msm/msm_gpu.h 	val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32);
gpu               256 drivers/gpu/drm/msm/msm_gpu.h static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val)
gpu               259 drivers/gpu/drm/msm/msm_gpu.h 	msm_writel(lower_32_bits(val), gpu->mmio + (lo << 2));
gpu               260 drivers/gpu/drm/msm/msm_gpu.h 	msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2));
gpu               263 drivers/gpu/drm/msm/msm_gpu.h int msm_gpu_pm_suspend(struct msm_gpu *gpu);
gpu               264 drivers/gpu/drm/msm/msm_gpu.h int msm_gpu_pm_resume(struct msm_gpu *gpu);
gpu               265 drivers/gpu/drm/msm/msm_gpu.h void msm_gpu_resume_devfreq(struct msm_gpu *gpu);
gpu               267 drivers/gpu/drm/msm/msm_gpu.h int msm_gpu_hw_init(struct msm_gpu *gpu);
gpu               269 drivers/gpu/drm/msm/msm_gpu.h void msm_gpu_perfcntr_start(struct msm_gpu *gpu);
gpu               270 drivers/gpu/drm/msm/msm_gpu.h void msm_gpu_perfcntr_stop(struct msm_gpu *gpu);
gpu               271 drivers/gpu/drm/msm/msm_gpu.h int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
gpu               274 drivers/gpu/drm/msm/msm_gpu.h void msm_gpu_retire(struct msm_gpu *gpu);
gpu               275 drivers/gpu/drm/msm/msm_gpu.h void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
gpu               279 drivers/gpu/drm/msm/msm_gpu.h 		struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
gpu               282 drivers/gpu/drm/msm/msm_gpu.h void msm_gpu_cleanup(struct msm_gpu *gpu);
gpu               294 drivers/gpu/drm/msm/msm_gpu.h static inline struct msm_gpu_state *msm_gpu_crashstate_get(struct msm_gpu *gpu)
gpu               298 drivers/gpu/drm/msm/msm_gpu.h 	mutex_lock(&gpu->dev->struct_mutex);
gpu               300 drivers/gpu/drm/msm/msm_gpu.h 	if (gpu->crashstate) {
gpu               301 drivers/gpu/drm/msm/msm_gpu.h 		kref_get(&gpu->crashstate->ref);
gpu               302 drivers/gpu/drm/msm/msm_gpu.h 		state = gpu->crashstate;
gpu               305 drivers/gpu/drm/msm/msm_gpu.h 	mutex_unlock(&gpu->dev->struct_mutex);
gpu               310 drivers/gpu/drm/msm/msm_gpu.h static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu)
gpu               312 drivers/gpu/drm/msm/msm_gpu.h 	mutex_lock(&gpu->dev->struct_mutex);
gpu               314 drivers/gpu/drm/msm/msm_gpu.h 	if (gpu->crashstate) {
gpu               315 drivers/gpu/drm/msm/msm_gpu.h 		if (gpu->funcs->gpu_state_put(gpu->crashstate))
gpu               316 drivers/gpu/drm/msm/msm_gpu.h 			gpu->crashstate = NULL;
gpu               319 drivers/gpu/drm/msm/msm_gpu.h 	mutex_unlock(&gpu->dev->struct_mutex);
gpu                89 drivers/gpu/drm/msm/msm_gpu_trace.h #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/msm
gpu                13 drivers/gpu/drm/msm/msm_gpummu.c 	struct msm_gpu *gpu;
gpu                58 drivers/gpu/drm/msm/msm_gpummu.c 	gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE,
gpu                73 drivers/gpu/drm/msm/msm_gpummu.c 	gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE,
gpu                97 drivers/gpu/drm/msm/msm_gpummu.c struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu)
gpu               112 drivers/gpu/drm/msm/msm_gpummu.c 	gpummu->gpu = gpu;
gpu                36 drivers/gpu/drm/msm/msm_mmu.h struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu);
gpu                61 drivers/gpu/drm/msm/msm_perf.c 	struct msm_gpu *gpu = priv->gpu;
gpu                72 drivers/gpu/drm/msm/msm_perf.c 		for (i = 0; i < gpu->num_perfcntrs; i++) {
gpu                73 drivers/gpu/drm/msm/msm_perf.c 			const struct msm_gpu_perfcntr *perfcntr = &gpu->perfcntrs[i];
gpu                90 drivers/gpu/drm/msm/msm_perf.c 		ret = msm_gpu_perfcntr_sample(gpu, &activetime, &totaltime,
gpu               155 drivers/gpu/drm/msm/msm_perf.c 	struct msm_gpu *gpu = priv->gpu;
gpu               160 drivers/gpu/drm/msm/msm_perf.c 	if (perf->open || !gpu) {
gpu               170 drivers/gpu/drm/msm/msm_perf.c 	msm_gpu_perfcntr_start(gpu);
gpu               182 drivers/gpu/drm/msm/msm_perf.c 	msm_gpu_perfcntr_stop(priv->gpu);
gpu               179 drivers/gpu/drm/msm/msm_rd.c 	struct msm_gpu *gpu = priv->gpu;
gpu               186 drivers/gpu/drm/msm/msm_rd.c 	if (rd->open || !gpu) {
gpu               197 drivers/gpu/drm/msm/msm_rd.c 	gpu->funcs->get_param(gpu, MSM_PARAM_GPU_ID, &val);
gpu                10 drivers/gpu/drm/msm/msm_ringbuffer.c struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id,
gpu                26 drivers/gpu/drm/msm/msm_ringbuffer.c 	ring->gpu = gpu;
gpu                29 drivers/gpu/drm/msm/msm_ringbuffer.c 	ring->start = msm_gem_kernel_new(gpu->dev, MSM_GPU_RINGBUFFER_SZ,
gpu                30 drivers/gpu/drm/msm/msm_ringbuffer.c 		MSM_BO_WC, gpu->aspace, &ring->bo, &ring->iova);
gpu                52 drivers/gpu/drm/msm/msm_ringbuffer.c 	ring->fctx = msm_fence_context_alloc(gpu->dev, name);
gpu                68 drivers/gpu/drm/msm/msm_ringbuffer.c 	msm_gem_kernel_put(ring->bo, ring->gpu->aspace, false);
gpu                37 drivers/gpu/drm/msm/msm_ringbuffer.h 	struct msm_gpu *gpu;
gpu                51 drivers/gpu/drm/msm/msm_ringbuffer.h struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id,
gpu                73 drivers/gpu/drm/msm/msm_submitqueue.c 	if (priv->gpu) {
gpu                74 drivers/gpu/drm/msm/msm_submitqueue.c 		if (prio >= priv->gpu->nr_rings)
gpu               106 drivers/gpu/drm/msm/msm_submitqueue.c 	default_prio = priv->gpu ?
gpu               107 drivers/gpu/drm/msm/msm_submitqueue.c 		clamp_t(uint32_t, 2, 0, priv->gpu->nr_rings - 1) : 0;
gpu               208 drivers/gpu/drm/radeon/radeon_trace.h #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/radeon
gpu               103 drivers/gpu/drm/scheduler/gpu_scheduler_trace.h #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/scheduler
gpu                66 drivers/gpu/drm/tegra/trace.h #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/tegra
gpu                59 drivers/gpu/drm/vc4/vc4_trace.h #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/vc4
gpu                51 drivers/gpu/drm/virtio/virtgpu_trace.h #define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/virtio
gpu              5274 drivers/pci/quirks.c static void quirk_nvidia_hda(struct pci_dev *gpu)
gpu              5280 drivers/pci/quirks.c 	if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M)
gpu              5284 drivers/pci/quirks.c 	pci_read_config_dword(gpu, 0x488, &val);
gpu              5288 drivers/pci/quirks.c 	pci_info(gpu, "Enabling HDA controller\n");
gpu              5289 drivers/pci/quirks.c 	pci_write_config_dword(gpu, 0x488, val | BIT(25));
gpu              5292 drivers/pci/quirks.c 	pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type);
gpu              5293 drivers/pci/quirks.c 	gpu->multifunction = !!(hdr_type & 0x80);
gpu              1430 drivers/pinctrl/actions/pinctrl-s900.c 	[S900_MUX_GPU] = FUNCTION(gpu),
gpu              2074 drivers/pinctrl/tegra/pinctrl-tegra20.c 	MUX_PG(gpu,    PWM,       UARTA,     GMI,       RSVD4,         0x14, 16, 0x8c, 4,  0xa4, 20),
gpu               271 drivers/video/fbdev/vermilion/vermilion.c 	par->gpu = pci_get_device(PCI_VENDOR_ID_INTEL, VML_DEVICE_GPU, NULL);
gpu               273 drivers/video/fbdev/vermilion/vermilion.c 	if (!par->gpu) {
gpu               280 drivers/video/fbdev/vermilion/vermilion.c 	if (pci_enable_device(par->gpu) < 0)
gpu               328 drivers/video/fbdev/vermilion/vermilion.c 	par->gpu_mem_base = pci_resource_start(par->gpu, 0);
gpu               329 drivers/video/fbdev/vermilion/vermilion.c 	par->gpu_mem_size = pci_resource_len(par->gpu, 0);
gpu               372 drivers/video/fbdev/vermilion/vermilion.c 		pci_disable_device(par->gpu);
gpu               183 drivers/video/fbdev/vermilion/vermilion.h 	struct pci_dev *gpu;