gpt_base 21 arch/arm/mach-mediatek/mediatek.c void __iomem *gpt_base; gpt_base 28 arch/arm/mach-mediatek/mediatek.c gpt_base = ioremap(GPT6_CON_MT65xx, 0x04); gpt_base 31 arch/arm/mach-mediatek/mediatek.c writel(GPT_ENABLE, gpt_base); gpt_base 32 arch/arm/mach-mediatek/mediatek.c iounmap(gpt_base); gpt_base 66 arch/arm/mach-spear/time.c static __iomem void *gpt_base; gpt_base 78 arch/arm/mach-spear/time.c writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC)); gpt_base 84 arch/arm/mach-spear/time.c writew(0xFFFF, gpt_base + LOAD(CLKSRC)); gpt_base 86 arch/arm/mach-spear/time.c val = readw(gpt_base + CR(CLKSRC)); gpt_base 89 arch/arm/mach-spear/time.c writew(val, gpt_base + CR(CLKSRC)); gpt_base 92 arch/arm/mach-spear/time.c clocksource_mmio_init(gpt_base + COUNT(CLKSRC), "tmr1", tick_rate, gpt_base 98 arch/arm/mach-spear/time.c u16 val = readw(gpt_base + CR(CLKEVT)); gpt_base 102 arch/arm/mach-spear/time.c writew(val, gpt_base + CR(CLKEVT)); gpt_base 119 arch/arm/mach-spear/time.c val = readw(gpt_base + CR(CLKEVT)); gpt_base 121 arch/arm/mach-spear/time.c writew(val, gpt_base + CR(CLKEVT)); gpt_base 136 arch/arm/mach-spear/time.c writew(period, gpt_base + LOAD(CLKEVT)); gpt_base 138 arch/arm/mach-spear/time.c val = readw(gpt_base + CR(CLKEVT)); gpt_base 141 arch/arm/mach-spear/time.c writew(val, gpt_base + CR(CLKEVT)); gpt_base 160 arch/arm/mach-spear/time.c u16 val = readw(gpt_base + CR(CLKEVT)); gpt_base 163 arch/arm/mach-spear/time.c writew(val & ~CTRL_ENABLE, gpt_base + CR(CLKEVT)); gpt_base 165 arch/arm/mach-spear/time.c writew(cycles, gpt_base + LOAD(CLKEVT)); gpt_base 168 arch/arm/mach-spear/time.c writew(val, gpt_base + CR(CLKEVT)); gpt_base 177 arch/arm/mach-spear/time.c writew(INT_STATUS, gpt_base + IR(CLKEVT)); gpt_base 195 arch/arm/mach-spear/time.c writew(CTRL_PRESCALER16, gpt_base + CR(CLKEVT)); gpt_base 229 arch/arm/mach-spear/time.c gpt_base = of_iomap(np, 0); gpt_base 230 arch/arm/mach-spear/time.c if (!gpt_base) { gpt_base 255 arch/arm/mach-spear/time.c iounmap(gpt_base);