gpc_base           30 arch/arm/mach-imx/gpc.c static void __iomem *gpc_base;
gpc_base           37 arch/arm/mach-imx/gpc.c 		(sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PUPSCR);
gpc_base           43 arch/arm/mach-imx/gpc.c 		(sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PDNSCR);
gpc_base           48 arch/arm/mach-imx/gpc.c 	writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN);
gpc_base           55 arch/arm/mach-imx/gpc.c 	val = readl_relaxed(gpc_base + GPC_CNTR);
gpc_base           59 arch/arm/mach-imx/gpc.c 	writel_relaxed(val, gpc_base + GPC_CNTR);
gpc_base           64 arch/arm/mach-imx/gpc.c 	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
gpc_base           79 arch/arm/mach-imx/gpc.c 	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
gpc_base          107 arch/arm/mach-imx/gpc.c 	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
gpc_base          119 arch/arm/mach-imx/gpc.c 	void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
gpc_base          131 arch/arm/mach-imx/gpc.c 	reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
gpc_base          142 arch/arm/mach-imx/gpc.c 	reg = gpc_base + GPC_IMR1 + hwirq / 32 * 4;
gpc_base          245 arch/arm/mach-imx/gpc.c 	gpc_base = of_iomap(node, 0);
gpc_base          246 arch/arm/mach-imx/gpc.c 	if (WARN_ON(!gpc_base))
gpc_base          253 arch/arm/mach-imx/gpc.c 		iounmap(gpc_base);
gpc_base          259 arch/arm/mach-imx/gpc.c 		writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
gpc_base          283 arch/arm/mach-imx/gpc.c 		gpc_base = of_iomap(np, 0);
gpc_base          135 arch/arm/mach-imx/pm-imx5.c static void __iomem *gpc_base;
gpc_base          154 arch/arm/mach-imx/pm-imx5.c 	arm_srpgcr = imx_readl(gpc_base + MXC_SRPG_ARM_SRPGCR) &
gpc_base          156 arch/arm/mach-imx/pm-imx5.c 	empgc0 = imx_readl(gpc_base + MXC_SRPG_EMPGC0_SRPGCR) &
gpc_base          158 arch/arm/mach-imx/pm-imx5.c 	empgc1 = imx_readl(gpc_base + MXC_SRPG_EMPGC1_SRPGCR) &
gpc_base          195 arch/arm/mach-imx/pm-imx5.c 	imx_writel(arm_srpgcr, gpc_base + MXC_SRPG_ARM_SRPGCR);
gpc_base          196 arch/arm/mach-imx/pm-imx5.c 	imx_writel(arm_srpgcr, gpc_base + MXC_SRPG_NEON_SRPGCR);
gpc_base          202 arch/arm/mach-imx/pm-imx5.c 		imx_writel(empgc0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR);
gpc_base          203 arch/arm/mach-imx/pm-imx5.c 		imx_writel(empgc1, gpc_base + MXC_SRPG_EMPGC1_SRPGCR);
gpc_base          225 arch/arm/mach-imx/pm-imx5.c 		imx_writel(0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR);
gpc_base          226 arch/arm/mach-imx/pm-imx5.c 		imx_writel(0, gpc_base + MXC_SRPG_EMPGC1_SRPGCR);
gpc_base          388 arch/arm/mach-imx/pm-imx5.c 	gpc_base = ioremap(data->gpc_addr, SZ_16K);
gpc_base          389 arch/arm/mach-imx/pm-imx5.c 	WARN_ON(!ccm_base || !cortex_base || !gpc_base);
gpc_base          225 arch/arm/mach-imx/pm-imx6.c 	struct imx6_pm_base gpc_base;
gpc_base          541 arch/arm/mach-imx/pm-imx6.c 	ret = imx6_pm_get_base(&pm_info->gpc_base, socdata->gpc_compat);
gpc_base          576 arch/arm/mach-imx/pm-imx6.c 	iounmap(pm_info->gpc_base.vbase);
gpc_base           23 drivers/irqchip/irq-imx-gpcv2.c 	void __iomem		*gpc_base;
gpc_base           33 drivers/irqchip/irq-imx-gpcv2.c 	return cd->gpc_base + cd->cpu2wakeup + i * 4;
gpc_base          238 drivers/irqchip/irq-imx-gpcv2.c 	cd->gpc_base = of_iomap(node, 0);
gpc_base          239 drivers/irqchip/irq-imx-gpcv2.c 	if (!cd->gpc_base) {
gpc_base          248 drivers/irqchip/irq-imx-gpcv2.c 		iounmap(cd->gpc_base);
gpc_base          256 drivers/irqchip/irq-imx-gpcv2.c 		void __iomem *reg = cd->gpc_base + i * 4;
gpc_base          278 drivers/irqchip/irq-imx-gpcv2.c 	writel_relaxed(~0x1, cd->gpc_base + cd->cpu2wakeup);