gpc 129 arch/arm/mach-imx/cpu-imx5.c u32 gpc; gpc 151 arch/arm/mach-imx/cpu-imx5.c gpc = readl_relaxed(tigerp_base + ARM_GPC); gpc 152 arch/arm/mach-imx/cpu-imx5.c gpc |= DBGEN; gpc 153 arch/arm/mach-imx/cpu-imx5.c writel_relaxed(gpc, tigerp_base + ARM_GPC); gpc 81 arch/arm/plat-samsung/include/plat/gpio-core.h static inline struct samsung_gpio_chip *to_samsung_gpio(struct gpio_chip *gpc) gpc 83 arch/arm/plat-samsung/include/plat/gpio-core.h return container_of(gpc, struct samsung_gpio_chip, chip); gpc 37 drivers/gpu/drm/nouveau/include/nvif/ifc00d.h __u8 gpc; gpc 26 drivers/gpu/drm/nouveau/include/nvkm/subdev/fault.h u8 gpc; gpc 59 drivers/gpu/drm/nouveau/nouveau_svm.c u8 gpc; gpc 397 drivers/gpu/drm/nouveau/nouveau_svm.c u64 inst, u8 hub, u8 gpc, u8 client) gpc 399 drivers/gpu/drm/nouveau/nouveau_svm.c SVM_DBG(svm, "cancel %016llx %d %02x %02x", inst, hub, gpc, client); gpc 404 drivers/gpu/drm/nouveau/nouveau_svm.c .gpc = gpc, gpc 416 drivers/gpu/drm/nouveau/nouveau_svm.c fault->gpc, gpc 449 drivers/gpu/drm/nouveau/nouveau_svm.c const u8 gpc = (info & 0x1f000000) >> 24; gpc 463 drivers/gpu/drm/nouveau/nouveau_svm.c nouveau_svm_fault_cancel(svm, inst, hub, gpc, client); gpc 474 drivers/gpu/drm/nouveau/nouveau_svm.c fault->gpc = gpc; gpc 274 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c snprintf(gpcid, sizeof(gpcid), "GPC%d/", info->gpc); gpc 387 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c info.gpc = (type & 0x1f000000) >> 24; gpc 483 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c snprintf(ct, sizeof(ct), "GPC%d/", info->gpc); gpc 86 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c info.gpc = (type & 0x1f000000) >> 24; gpc 70 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c info.gpc = (type & 0x1f000000) >> 24; gpc 1072 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c int gpc, tpc; gpc 1079 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gpc 1080 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { gpc 1081 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c const u32 o = TPC_UNIT(gpc, tpc, 0x0520); gpc 1106 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c data |= gr->sm[sm++].gpc << (j * 8); gpc 1275 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c int i, gpc; gpc 1287 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c for (gpc = 0; atarget && gpc < gr->gpc_nr; gpc++) { gpc 1288 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c if (abits[gpc] < gr->tpc_nr[gpc]) { gpc 1289 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c abits[gpc]++; gpc 1295 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gpc 1296 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c u32 bbits = gr->tpc_nr[gpc] - abits[gpc]; gpc 1297 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c amask |= ((1 << abits[gpc]) - 1) << (gpc * 8); gpc 1298 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c bmask |= ((1 << bbits) - 1) << abits[gpc] << (gpc * 8); gpc 1307 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_grctx_generate_tpc_nr(struct gf100_gr *gr, int gpc) gpc 1310 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c nvkm_wr32(device, GPC_UNIT(gpc, 0x0c08), gr->tpc_nr[gpc]); gpc 1311 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c nvkm_wr32(device, GPC_UNIT(gpc, 0x0c8c), gr->tpc_nr[gpc]); gpc 1315 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c gf100_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) gpc 1318 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x698), sm); gpc 1319 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x4e8), sm); gpc 1320 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), sm); gpc 1321 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm); gpc 1329 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c int gpc, sm, i, j; gpc 1333 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c func->sm_id(gr, gr->sm[sm].gpc, gr->sm[sm].tpc, sm); gpc 1335 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c func->tpc_nr(gr, gr->sm[sm].gpc); gpc 1338 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c for (gpc = 0, i = 0; i < 4; i++) { gpc 1339 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c for (data = 0, j = 0; j < 8 && gpc < gr->gpc_nr; j++, gpc++) gpc 1340 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c data |= gr->tpc_nr[gpc] << (j * 4); gpc 58 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h void (*sm_id)(struct gf100_gr *, int gpc, int tpc, int sm); gpc 59 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h void (*tpc_nr)(struct gf100_gr *, int gpc); gpc 749 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c int gpc, tpc; gpc 756 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gpc 757 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { gpc 761 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c const u32 o = TPC_UNIT(gpc, tpc, 0x500); gpc 257 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c int gpc, ppc; gpc 264 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gpc 265 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) { gpc 266 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c const u32 a = alpha * gr->ppc_tpc_nr[gpc][ppc]; gpc 267 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c const u32 b = beta * gr->ppc_tpc_nr[gpc][ppc]; gpc 269 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c const u32 o = PPC_UNIT(gpc, ppc, 0); gpc 270 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c if (!(gr->ppc_mask[gpc] & (1 << ppc))) gpc 274 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; gpc 276 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; gpc 933 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c int i, j, gpc, ppc; gpc 941 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gpc 943 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c u32 ppc_tpcs = gr->ppc_tpc_nr[gpc][ppc]; gpc 954 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c pmask = gr->ppc_tpc_mask[gpc][ppc]; gpc 957 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c amask |= (u64)pmask << (gpc * 8); gpc 959 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c pmask ^= gr->ppc_tpc_mask[gpc][ppc]; gpc 960 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c bmask |= (u64)pmask << (gpc * 8); gpc 921 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c int gpc, ppc, n = 0; gpc 929 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gpc 930 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { gpc 931 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; gpc 932 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc]; gpc 934 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c const u32 o = PPC_UNIT(gpc, ppc, 0); gpc 935 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c if (!(gr->ppc_mask[gpc] & (1 << ppc))) gpc 939 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; gpc 942 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; gpc 955 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c gm107_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) gpc 958 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x698), sm); gpc 959 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), sm); gpc 960 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm); gpc 55 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c const u8 gpc = gr->sm[sm].gpc; gpc 57 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c dist[sm / 4] |= ((gpc << 4) | tpc) << ((sm % 4) * 8); gpc 58 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c gpcs[gpc] |= sm << (tpc * 8); gpc 87 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c int gpc, ppc, i; gpc 89 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gpc 90 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) { gpc 91 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c u8 ppc_tpcs = gr->ppc_tpc_nr[gpc][ppc]; gpc 92 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c u8 ppc_tpcm = gr->ppc_tpc_mask[gpc][ppc]; gpc 95 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c ppc_tpcm ^= gr->ppc_tpc_mask[gpc][ppc]; gpc 96 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.c ((u8 *)data)[gpc] |= ppc_tpcm; gpc 56 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c int gpc, ppc, b, n = 0; gpc 58 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) gpc 59 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c size += grctx->attrib_nr_max * gr->ppc_nr[gpc] * gr->ppc_tpc_max; gpc 72 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gpc 73 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { gpc 74 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; gpc 77 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c const u32 o = PPC_UNIT(gpc, ppc, 0); gpc 78 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c if (!(gr->ppc_mask[gpc] & (1 << ppc))) gpc 86 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; gpc 104 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c const u8 gpc = gr->sm[sm].gpc; gpc 106 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c dist[sm / 4] |= ((gpc << 4) | tpc) << ((sm % 4) * 8); gpc 107 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c gpcs[gpc + (gr->func->gpc_nr * (tpc / 4))] |= sm << ((tpc % 4) * 8); gpc 52 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c int gpc, ppc, b, n = 0; gpc 54 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) gpc 55 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c size += grctx->gfxp_nr * gr->ppc_nr[gpc] * gr->ppc_tpc_max; gpc 68 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gpc 69 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { gpc 70 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; gpc 74 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c const u32 o = PPC_UNIT(gpc, ppc, 0); gpc 75 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c const u32 p = GPC_UNIT(gpc, 0xc44 + (ppc * 4)); gpc 76 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c if (!(gr->ppc_mask[gpc] & (1 << ppc))) gpc 85 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; gpc 74 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c int gpc, ppc, b, n = 0; gpc 89 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gpc 90 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { gpc 91 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; gpc 92 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc]; gpc 93 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c const u32 gs = gfxp * gr->ppc_tpc_nr[gpc][ppc]; gpc 95 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c const u32 o = PPC_UNIT(gpc, ppc, 0); gpc 96 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c if (!(gr->ppc_mask[gpc] & (1 << ppc))) gpc 104 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; gpc 158 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c gv100_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) gpc 161 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm); gpc 162 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), sm); gpc 163 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm); gpc 1174 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc) gpc 1181 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff; gpc 1182 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434)); gpc 1183 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438)); gpc 1184 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c)); gpc 1190 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gpc, trap[0], error, trap[1] & 0xffff, trap[1] >> 16, gpc 1192 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); gpc 1235 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) gpc 1239 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648)); gpc 1240 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650)); gpc 1249 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gpc, tpc, gerr, glob, werr, warp ? warp->name : ""); gpc 1251 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x648), 0x00000000); gpc 1252 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x650), gerr); gpc 1256 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc) gpc 1260 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 stat = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0508)); gpc 1263 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0224)); gpc 1264 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_error(subdev, "GPC%d/TPC%d/TEX: %08x\n", gpc, tpc, trap); gpc 1265 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000); gpc 1270 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->trap_mp(gr, gpc, tpc); gpc 1275 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0084)); gpc 1276 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_error(subdev, "GPC%d/TPC%d/POLY: %08x\n", gpc, tpc, trap); gpc 1277 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000); gpc 1282 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x048c)); gpc 1283 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_error(subdev, "GPC%d/TPC%d/L1C: %08x\n", gpc, tpc, trap); gpc 1284 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000); gpc 1289 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0430)); gpc 1290 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_error(subdev, "GPC%d/TPC%d/MPC: %08x\n", gpc, tpc, trap); gpc 1291 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0430), 0xc0000000); gpc 1296 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_error(subdev, "GPC%d/TPC%d/%08x: unknown\n", gpc, tpc, stat); gpc 1301 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc) gpc 1305 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 stat = nvkm_rd32(device, GPC_UNIT(gpc, 0x2c90)); gpc 1309 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_trap_gpc_rop(gr, gpc); gpc 1314 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0900)); gpc 1315 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_error(subdev, "GPC%d/ZCULL: %08x\n", gpc, trap); gpc 1316 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); gpc 1321 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x1028)); gpc 1322 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_error(subdev, "GPC%d/CCACHE: %08x\n", gpc, trap); gpc 1323 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); gpc 1328 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0824)); gpc 1329 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_error(subdev, "GPC%d/ESETUP: %08x\n", gpc, trap); gpc 1330 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); gpc 1334 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { gpc 1337 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_trap_tpc(gr, gpc, tpc); gpc 1338 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), mask); gpc 1344 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_error(subdev, "GPC%d/%08x: unknown\n", gpc, stat); gpc 1355 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c int rop, gpc; gpc 1443 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (gpc = 0; stat && gpc < gr->gpc_nr; gpc++) { gpc 1444 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 mask = 0x00000001 << gpc; gpc 1446 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_trap_gpc(gr, gpc); gpc 1498 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u32 gpc; gpc 1501 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (gpc = 0; gpc < gpcnr; gpc++) gpc 1502 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_ctxctl_debug_unit(gr, 0x502000 + (gpc * 0x8000)); gpc 1849 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c int tpc, gpc; gpc 1851 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gpc 1852 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (tpc < gr->tpc_nr[gpc]) { gpc 1853 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->sm[gr->sm_nr].gpc = gpc; gpc 2207 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) gpc 2210 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); gpc 2211 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); gpc 2215 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_init_tex_hww_esr(struct gf100_gr *gr, int gpc, int tpc) gpc 2218 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); gpc 2232 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c int gpc, tpc; gpc 2236 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gpc 2237 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) gpc 2238 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); gpc 2284 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c u8 bank[GPC_MAX] = {}, gpc, i, j; gpc 2295 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gpc 2296 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), gpc 2297 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); gpc 2298 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | gpc 2300 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); gpc 2317 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c int gpc, tpc, rop; gpc 2386 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gpc 2387 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); gpc 2388 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); gpc 2389 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); gpc 2390 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); gpc 2391 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { gpc 2392 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); gpc 2393 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); gpc 2395 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->init_tex_hww_esr(gr, gpc, tpc); gpc 2396 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); gpc 2398 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->init_504430(gr, gpc, tpc); gpc 2399 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->init_shader_exceptions(gr, gpc, tpc); gpc 2401 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff); gpc 2402 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff); gpc 130 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h u8 gpc; gpc 182 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h void (*init_tex_hww_esr)(struct gf100_gr *, int gpc, int tpc); gpc 183 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h void (*init_504430)(struct gf100_gr *, int gpc, int tpc); gpc 184 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h void (*init_shader_exceptions)(struct gf100_gr *, int gpc, int tpc); gpc 187 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h void (*trap_mp)(struct gf100_gr *, int gpc, int tpc); gpc 129 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c u8 bank[GPC_MAX] = {}, gpc, i, j; gpc 140 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gpc 141 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), gpc 142 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); gpc 143 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | gpc 145 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); gpc 418 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c int gpc, ppc; gpc 420 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gpc 421 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) { gpc 422 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c if (!(gr->ppc_mask[gpc] & (1 << ppc))) gpc 424 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c nvkm_wr32(device, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000); gpc 294 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c gm107_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) gpc 297 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); gpc 298 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005); gpc 302 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c gm107_gr_init_504430(struct gf100_gr *gr, int gpc, int tpc) gpc 305 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000); gpc 72 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c gp100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) gpc 75 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); gpc 76 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000105); gpc 89 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c u32 mask = 0, data, gpc; gpc 91 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c for (gpc = 0; gpc < gr->gpc_nr; gpc++) { gpc 92 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c data = nvkm_rd32(device, GPC_UNIT(gpc, 0x0c50)) & 0x0000000f; gpc 93 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c mask |= data << (gpc * 4); gpc 28 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c gv100_gr_trap_sm(struct gf100_gr *gr, int gpc, int tpc, int sm) gpc 32 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x730 + (sm * 0x80))); gpc 33 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x734 + (sm * 0x80))); gpc 42 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c gpc, tpc, sm, gerr, glob, werr, warp ? warp->name : ""); gpc 44 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x730 + sm * 0x80), 0x00000000); gpc 45 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x734 + sm * 0x80), gerr); gpc 49 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c gv100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) gpc 51 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c gv100_gr_trap_sm(gr, gpc, tpc, 0); gpc 52 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c gv100_gr_trap_sm(gr, gpc, tpc, 1); gpc 63 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c gv100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) gpc 68 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x728 + sm), 0x0085eb64); gpc 69 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x610), 0x00000001); gpc 70 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x72c + sm), 0x00000004); gpc 75 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c gv100_gr_init_504430(struct gf100_gr *gr, int gpc, int tpc) gpc 78 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0x403f0000); gpc 62 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c info.gpc = (info1 & 0x1f000000) >> 24; gpc 142 drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.c info.gpc = (info1 & 0x1f000000) >> 24; gpc 89 drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.c info.gpc = (info1 & 0x1f000000) >> 24; gpc 416 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c (args->v0.gpc << 15) | gpc 7613 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c u32 gpc; gpc 7618 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); gpc 7619 drivers/net/ethernet/intel/ixgbe/ixgbe_main.c if (gpc) /* If incrementing then no need for the check below */