gpa_mask           98 arch/ia64/include/asm/uv/uv_hub.h 	unsigned long	gpa_mask;
gpa_mask          168 arch/ia64/include/asm/uv/uv_hub.h 	return __va(gpa & uv_hub_info->gpa_mask);
gpa_mask          113 arch/ia64/uv/kernel/setup.c 		uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
gpa_mask          159 arch/x86/include/asm/uv/uv_hub.h 	unsigned long		gpa_mask;
gpa_mask          457 arch/x86/include/asm/uv/uv_hub.h 	unsigned long pal = (pa & uv_hub_info->gpa_mask) >> UV_GAM_RANGE_SHFT;
gpa_mask          541 arch/x86/include/asm/uv/uv_hub.h 	paddr = gpa & uv_hub_info->gpa_mask;
gpa_mask          572 arch/x86/include/asm/uv/uv_hub.h 	return (gpa & uv_hub_info->gpa_mask) - uv_gam_range_base(gpa);
gpa_mask         1138 arch/x86/kernel/apic/x2apic_uv_x.c 	hi->gpa_mask = mn.m_val ?
gpa_mask         1168 arch/x86/kernel/apic/x2apic_uv_x.c 		hi->gpa_mask		= (1UL << hi->gpa_shift) - 1;
gpa_mask         1180 arch/x86/kernel/apic/x2apic_uv_x.c 	pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift);