gmch_m 947 drivers/gpu/drm/gma500/cdv_intel_dp.c uint32_t gmch_m; gmch_m 977 drivers/gpu/drm/gma500/cdv_intel_dp.c m_n->gmch_m = (pixel_clock * bpp + 7) >> 3; gmch_m 979 drivers/gpu/drm/gma500/cdv_intel_dp.c cdv_intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); gmch_m 1031 drivers/gpu/drm/gma500/cdv_intel_dp.c m_n.gmch_m); gmch_m 7537 drivers/gpu/drm/i915/display/intel_display.c &m_n->gmch_m, &m_n->gmch_n, gmch_m 7626 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); gmch_m 7655 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); gmch_m 7666 drivers/gpu/drm/i915/display/intel_display.c TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); gmch_m 7672 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); gmch_m 9698 drivers/gpu/drm/i915/display/intel_display.c m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) gmch_m 9716 drivers/gpu/drm/i915/display/intel_display.c m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) gmch_m 9725 drivers/gpu/drm/i915/display/intel_display.c m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) gmch_m 9734 drivers/gpu/drm/i915/display/intel_display.c m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) gmch_m 11970 drivers/gpu/drm/i915/display/intel_display.c m_n->gmch_m, m_n->gmch_n, gmch_m 12465 drivers/gpu/drm/i915/display/intel_display.c intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, gmch_m 12466 drivers/gpu/drm/i915/display/intel_display.c m2_n2->gmch_m, m2_n2->gmch_n, exact) && gmch_m 12618 drivers/gpu/drm/i915/display/intel_display.c current_config->name.gmch_m, \ gmch_m 12623 drivers/gpu/drm/i915/display/intel_display.c pipe_config->name.gmch_m, \ gmch_m 12646 drivers/gpu/drm/i915/display/intel_display.c current_config->name.gmch_m, \ gmch_m 12651 drivers/gpu/drm/i915/display/intel_display.c current_config->alt_name.gmch_m, \ gmch_m 12656 drivers/gpu/drm/i915/display/intel_display.c pipe_config->name.gmch_m, \ gmch_m 261 drivers/gpu/drm/i915/display/intel_display.h u32 gmch_m;