glb_base          207 drivers/dma/sprd-dma.c 	void __iomem		*glb_base;
glb_base          241 drivers/dma/sprd-dma.c 	u32 orig = readl(sdev->glb_base + reg);
glb_base          245 drivers/dma/sprd-dma.c 	writel(tmp, sdev->glb_base + reg);
glb_base          296 drivers/dma/sprd-dma.c 		writel(schan->chn_num + 1, sdev->glb_base + uid_offset);
glb_base          309 drivers/dma/sprd-dma.c 		writel(0, sdev->glb_base + uid_offset);
glb_base          564 drivers/dma/sprd-dma.c 	u32 irq_status = readl(sdev->glb_base + SPRD_DMA_GLB_INT_MSK_STS);
glb_base         1130 drivers/dma/sprd-dma.c 	sdev->glb_base = devm_ioremap_resource(&pdev->dev, res);
glb_base         1131 drivers/dma/sprd-dma.c 	if (IS_ERR(sdev->glb_base))
glb_base         1132 drivers/dma/sprd-dma.c 		return PTR_ERR(sdev->glb_base);
glb_base         1156 drivers/dma/sprd-dma.c 		dma_chn->chn_base = sdev->glb_base + SPRD_DMA_CHN_REG_OFFSET +
glb_base          110 drivers/net/ethernet/hisilicon/hisi_femac.c 	void __iomem *glb_base;
glb_base          130 drivers/net/ethernet/hisilicon/hisi_femac.c 	val = readl(priv->glb_base + GLB_IRQ_ENA);
glb_base          131 drivers/net/ethernet/hisilicon/hisi_femac.c 	writel(val | irqs, priv->glb_base + GLB_IRQ_ENA);
glb_base          138 drivers/net/ethernet/hisilicon/hisi_femac.c 	val = readl(priv->glb_base + GLB_IRQ_ENA);
glb_base          139 drivers/net/ethernet/hisilicon/hisi_femac.c 	writel(val & (~irqs), priv->glb_base + GLB_IRQ_ENA);
glb_base          254 drivers/net/ethernet/hisilicon/hisi_femac.c 	while (readl(priv->glb_base + GLB_IRQ_RAW) & IRQ_INT_RX_RDY) {
glb_base          260 drivers/net/ethernet/hisilicon/hisi_femac.c 		writel(IRQ_INT_RX_RDY, priv->glb_base + GLB_IRQ_RAW);
glb_base          315 drivers/net/ethernet/hisilicon/hisi_femac.c 		ints = readl(priv->glb_base + GLB_IRQ_RAW);
glb_base          317 drivers/net/ethernet/hisilicon/hisi_femac.c 		       priv->glb_base + GLB_IRQ_RAW);
glb_base          335 drivers/net/ethernet/hisilicon/hisi_femac.c 	ints = readl(priv->glb_base + GLB_IRQ_RAW);
glb_base          339 drivers/net/ethernet/hisilicon/hisi_femac.c 		       priv->glb_base + GLB_IRQ_RAW);
glb_base          435 drivers/net/ethernet/hisilicon/hisi_femac.c 	writel(reg, priv->glb_base + GLB_HOSTMAC_H16);
glb_base          438 drivers/net/ethernet/hisilicon/hisi_femac.c 	writel(reg, priv->glb_base + GLB_HOSTMAC_L32);
glb_base          447 drivers/net/ethernet/hisilicon/hisi_femac.c 	val = readl(priv->glb_base + GLB_SOFT_RESET);
glb_base          449 drivers/net/ethernet/hisilicon/hisi_femac.c 	writel(val, priv->glb_base + GLB_SOFT_RESET);
glb_base          454 drivers/net/ethernet/hisilicon/hisi_femac.c 	writel(val, priv->glb_base + GLB_SOFT_RESET);
glb_base          476 drivers/net/ethernet/hisilicon/hisi_femac.c 	writel(IRQ_ENA_PORT0_MASK, priv->glb_base + GLB_IRQ_RAW);
glb_base          571 drivers/net/ethernet/hisilicon/hisi_femac.c 	val = readl(priv->glb_base + GLB_MAC_H16(reg_n));
glb_base          576 drivers/net/ethernet/hisilicon/hisi_femac.c 	writel(val, priv->glb_base + GLB_MAC_H16(reg_n));
glb_base          590 drivers/net/ethernet/hisilicon/hisi_femac.c 	writel(val, priv->glb_base + low);
glb_base          592 drivers/net/ethernet/hisilicon/hisi_femac.c 	val = readl(priv->glb_base + high);
glb_base          596 drivers/net/ethernet/hisilicon/hisi_femac.c 	writel(val, priv->glb_base + high);
glb_base          604 drivers/net/ethernet/hisilicon/hisi_femac.c 	val = readl(priv->glb_base + GLB_FWCTRL);
glb_base          609 drivers/net/ethernet/hisilicon/hisi_femac.c 	writel(val, priv->glb_base + GLB_FWCTRL);
glb_base          618 drivers/net/ethernet/hisilicon/hisi_femac.c 	val = readl(priv->glb_base + GLB_MACTCTRL);
glb_base          636 drivers/net/ethernet/hisilicon/hisi_femac.c 	writel(val, priv->glb_base + GLB_MACTCTRL);
glb_base          645 drivers/net/ethernet/hisilicon/hisi_femac.c 	val = readl(priv->glb_base + GLB_MACTCTRL);
glb_base          662 drivers/net/ethernet/hisilicon/hisi_femac.c 	writel(val, priv->glb_base + GLB_MACTCTRL);
glb_base          755 drivers/net/ethernet/hisilicon/hisi_femac.c 	writel(IRQ_ENA_PORT0_MASK, priv->glb_base + GLB_IRQ_RAW);
glb_base          758 drivers/net/ethernet/hisilicon/hisi_femac.c 	val = readl(priv->glb_base + GLB_FWCTRL);
glb_base          761 drivers/net/ethernet/hisilicon/hisi_femac.c 	writel(val, priv->glb_base + GLB_FWCTRL);
glb_base          763 drivers/net/ethernet/hisilicon/hisi_femac.c 	val = readl(priv->glb_base + GLB_MACTCTRL);
glb_base          765 drivers/net/ethernet/hisilicon/hisi_femac.c 	writel(val, priv->glb_base + GLB_MACTCTRL);
glb_base          807 drivers/net/ethernet/hisilicon/hisi_femac.c 	priv->glb_base = devm_platform_ioremap_resource(pdev, 1);
glb_base          808 drivers/net/ethernet/hisilicon/hisi_femac.c 	if (IS_ERR(priv->glb_base)) {
glb_base          809 drivers/net/ethernet/hisilicon/hisi_femac.c 		ret = PTR_ERR(priv->glb_base);
glb_base          109 drivers/phy/mediatek/phy-mtk-xsphy.c 	void __iomem *glb_base;	/* only shared u3 sif */
glb_base          347 drivers/phy/mediatek/phy-mtk-xsphy.c 		tmp = readl(xsphy->glb_base + SSPXTP_PHYA_GLB_00);
glb_base          350 drivers/phy/mediatek/phy-mtk-xsphy.c 		writel(tmp, xsphy->glb_base + SSPXTP_PHYA_GLB_00);
glb_base          519 drivers/phy/mediatek/phy-mtk-xsphy.c 		xsphy->glb_base = devm_ioremap_resource(dev, glb_res);
glb_base          520 drivers/phy/mediatek/phy-mtk-xsphy.c 		if (IS_ERR(xsphy->glb_base)) {
glb_base          522 drivers/phy/mediatek/phy-mtk-xsphy.c 			return PTR_ERR(xsphy->glb_base);