gim_int_lines      30 arch/arc/plat-eznps/platform.c 	u32 gim_int_lines;
gim_int_lines      33 arch/arc/plat-eznps/platform.c 	gim_int_lines = NPS_GIM_UART_LINE;
gim_int_lines      34 arch/arc/plat-eznps/platform.c 	gim_int_lines |= NPS_GIM_DBG_LAN_EAST_TX_DONE_LINE;
gim_int_lines      35 arch/arc/plat-eznps/platform.c 	gim_int_lines |= NPS_GIM_DBG_LAN_EAST_RX_RDY_LINE;
gim_int_lines      36 arch/arc/plat-eznps/platform.c 	gim_int_lines |= NPS_GIM_DBG_LAN_WEST_TX_DONE_LINE;
gim_int_lines      37 arch/arc/plat-eznps/platform.c 	gim_int_lines |= NPS_GIM_DBG_LAN_WEST_RX_RDY_LINE;
gim_int_lines      45 arch/arc/plat-eznps/platform.c 	reg_value &= ~gim_int_lines;
gim_int_lines      71 arch/arc/plat-eznps/platform.c 	iowrite32be(gim_int_lines, REG_GIM_P_INT_BLK_0);
gim_int_lines      74 arch/arc/plat-eznps/platform.c 	iowrite32be(gim_int_lines, REG_GIM_P_INT_EN_0);