gfx9 2734 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c input.swizzle_mode = tiling_info->gfx9.swizzle; gfx9 2864 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx9.num_pipes = gfx9 2866 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx9.num_banks = gfx9 2868 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx9.pipe_interleave = gfx9 2870 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx9.num_shader_engines = gfx9 2872 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx9.max_compressed_frags = gfx9 2874 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx9.num_rb_per_se = gfx9 2876 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx9.swizzle = gfx9 2878 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx9.shaderEnable = 1; gfx9 334 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle; gfx9 343 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.swizzle); gfx9 982 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c pipe->plane_state->tiling_info.gfx9.swizzle); gfx9 1452 drivers/gpu/drm/amd/display/dc/core/dc.c if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) { gfx9 171 drivers/gpu/drm/amd/display/dc/core/dc_debug.c plane_state->tiling_info.gfx9.swizzle); gfx9 257 drivers/gpu/drm/amd/display/dc/core/dc_debug.c update->plane_info->tiling_info.gfx9.swizzle); gfx9 2062 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) { gfx9 393 drivers/gpu/drm/amd/display/dc/dc_hw_types.h } gfx9; gfx9 360 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c GRPH_SW_MODE, info->gfx9.swizzle, gfx9 361 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c GRPH_NUM_BANKS, log_2(info->gfx9.num_banks), gfx9 362 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c GRPH_NUM_SHADER_ENGINES, log_2(info->gfx9.num_shader_engines), gfx9 363 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c GRPH_NUM_PIPES, log_2(info->gfx9.num_pipes), gfx9 365 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c GRPH_SE_ENABLE, info->gfx9.shaderEnable); gfx9 149 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c NUM_PIPES, log_2(info->gfx9.num_pipes), gfx9 150 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c NUM_BANKS, log_2(info->gfx9.num_banks), gfx9 151 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c PIPE_INTERLEAVE, info->gfx9.pipe_interleave, gfx9 152 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c NUM_SE, log_2(info->gfx9.num_shader_engines), gfx9 153 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se), gfx9 154 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); gfx9 157 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c SW_MODE, info->gfx9.swizzle, gfx9 158 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c META_LINEAR, info->gfx9.meta_linear, gfx9 159 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c RB_ALIGNED, info->gfx9.rb_aligned, gfx9 160 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c PIPE_ALIGNED, info->gfx9.pipe_aligned); gfx9 1211 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c plane_state->tiling_info.gfx9.swizzle = swizzle; gfx9 311 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c NUM_PIPES, log_2(info->gfx9.num_pipes), gfx9 312 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c PIPE_INTERLEAVE, info->gfx9.pipe_interleave, gfx9 313 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); gfx9 316 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c SW_MODE, info->gfx9.swizzle, gfx9 2130 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle); gfx9 2131 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle, gfx9 3000 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c plane_state->tiling_info.gfx9.swizzle = swizzle;