HDP_BASE           36 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c 		adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
HDP_BASE           36 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c 		adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
HDP_BASE           36 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c 		adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
HDP_BASE           36 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c 		adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
HDP_BASE           36 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c 		adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
HDP_BASE           36 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c 		adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
HDP_BASE           79 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE HDP_BASE            ={ { { { 0x00000F20, 0x00012520, 0x0040A400, 0, 0, 0 } },
HDP_BASE           73 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE HDP_BASE            ={ { { { 0x00000F20, 0, 0, 0, 0, 0 } },
HDP_BASE          102 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } },
HDP_BASE          102 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } },
HDP_BASE          116 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0x0240A400, 0, 0, 0 } },
HDP_BASE          158 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE HDP_BASE			= { { { { 0x00000F20, 0, 0, 0, 0 } },
HDP_BASE           75 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE HDP_BASE            ={ { { { 0x00000F20, 0, 0, 0, 0, 0 } },