HDMI_GENERIC_PACKET_CONTROL0 211 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC_PACKET_CONTROL0 217 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC_PACKET_CONTROL0 810 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0, HDMI_GENERIC_PACKET_CONTROL0 70 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \ HDMI_GENERIC_PACKET_CONTROL0 126 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\ HDMI_GENERIC_PACKET_CONTROL0 127 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\ HDMI_GENERIC_PACKET_CONTROL0 128 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\ HDMI_GENERIC_PACKET_CONTROL0 129 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\ HDMI_GENERIC_PACKET_CONTROL0 130 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\ HDMI_GENERIC_PACKET_CONTROL0 131 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h SE_SF(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh),\ HDMI_GENERIC_PACKET_CONTROL0 671 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h uint32_t HDMI_GENERIC_PACKET_CONTROL0; HDMI_GENERIC_PACKET_CONTROL0 189 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC_PACKET_CONTROL0 195 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC_PACKET_CONTROL0 672 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0, HDMI_GENERIC_PACKET_CONTROL0 58 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \ HDMI_GENERIC_PACKET_CONTROL0 140 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h uint32_t HDMI_GENERIC_PACKET_CONTROL0; HDMI_GENERIC_PACKET_CONTROL0 80 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC_PACKET_CONTROL0 87 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC_PACKET_CONTROL0 94 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC_PACKET_CONTROL0 101 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC_PACKET_CONTROL0 108 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC_PACKET_CONTROL0 115 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC_PACKET_CONTROL0 122 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC_PACKET_CONTROL0 129 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC_PACKET_CONTROL0 168 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, HDMI_GENERIC_PACKET_CONTROL0 178 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, HDMI_GENERIC_PACKET_CONTROL0 188 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0, HDMI_GENERIC_PACKET_CONTROL0 198 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,