gen_fifo_stat_reg   41 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c 	u32 gen_fifo_stat_reg = MIPI_GEN_FIFO_STAT_REG(pipe);
gen_fifo_stat_reg   48 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c 		(REG_READ(gen_fifo_stat_reg) & DSI_FIFO_GEN_HS_DATA_FULL)) {
gen_fifo_stat_reg   59 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c 	u32 gen_fifo_stat_reg = MIPI_GEN_FIFO_STAT_REG(pipe);
gen_fifo_stat_reg   65 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c 	while ((timeout < 20000) && (REG_READ(gen_fifo_stat_reg)
gen_fifo_stat_reg   76 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c 	u32 gen_fifo_stat_reg = MIPI_GEN_FIFO_STAT_REG(pipe);
gen_fifo_stat_reg   82 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c 	while ((timeout < 20000) && ((REG_READ(gen_fifo_stat_reg) &
gen_fifo_stat_reg   68 drivers/gpu/drm/gma500/mdfld_dsi_output.c void mdfld_dsi_gen_fifo_ready(struct drm_device *dev, u32 gen_fifo_stat_reg,
gen_fifo_stat_reg   77 drivers/gpu/drm/gma500/mdfld_dsi_output.c 		if ((REG_READ(gen_fifo_stat_reg) & fifo_stat) == fifo_stat)
gen_fifo_stat_reg   84 drivers/gpu/drm/gma500/mdfld_dsi_output.c 					gen_fifo_stat_reg);
gen_fifo_stat_reg  362 drivers/gpu/drm/gma500/mdfld_dsi_output.h 					u32 gen_fifo_stat_reg, u32 fifo_stat);
gen_fifo_stat_reg   86 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c 	u32 gen_fifo_stat_reg = sender->mipi_gen_fifo_stat_reg;
gen_fifo_stat_reg   90 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c 		if ((mask & REG_READ(gen_fifo_stat_reg)) == mask)
gen_fifo_stat_reg   94 drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c 	DRM_ERROR("fifo is NOT empty 0x%08x\n", REG_READ(gen_fifo_stat_reg));