gcu_status        150 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c static u64 get_pipeline_event(struct d71_pipeline *d71_pipeline, u32 gcu_status)
gcu_status        154 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c 	if (gcu_status & (GLB_IRQ_STATUS_LPU0 | GLB_IRQ_STATUS_LPU1))
gcu_status        157 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c 	if (gcu_status & (GLB_IRQ_STATUS_CU0 | GLB_IRQ_STATUS_CU1))
gcu_status        160 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c 	if (gcu_status & (GLB_IRQ_STATUS_DOU0 | GLB_IRQ_STATUS_DOU1))
gcu_status        170 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c 	u32 status, gcu_status, raw_status;
gcu_status        172 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c 	gcu_status = malidp_read32(d71->gcu_addr, GLB_IRQ_STATUS);
gcu_status        174 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c 	if (gcu_status & GLB_IRQ_STATUS_GCU) {
gcu_status        192 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c 	if (gcu_status & GLB_IRQ_STATUS_PIPE0)
gcu_status        193 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c 		evts->pipes[0] |= get_pipeline_event(d71->pipes[0], gcu_status);
gcu_status        195 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c 	if (gcu_status & GLB_IRQ_STATUS_PIPE1)
gcu_status        196 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c 		evts->pipes[1] |= get_pipeline_event(d71->pipes[1], gcu_status);
gcu_status        198 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c 	return gcu_status ? IRQ_HANDLED : IRQ_NONE;