gcu_addr          172 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c 	gcu_status = malidp_read32(d71->gcu_addr, GLB_IRQ_STATUS);
gcu_addr          175 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c 		raw_status = malidp_read32(d71->gcu_addr, BLK_IRQ_RAW_STATUS);
gcu_addr          181 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c 			status = malidp_read32(d71->gcu_addr, BLK_STATUS);
gcu_addr          184 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c 				malidp_write32_mask(d71->gcu_addr, BLK_STATUS,
gcu_addr          189 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c 		malidp_write32(d71->gcu_addr, BLK_IRQ_CLEAR, raw_status);
gcu_addr          213 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c 	malidp_write32_mask(d71->gcu_addr, BLK_IRQ_MASK,
gcu_addr          233 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c 	malidp_write32_mask(d71->gcu_addr, BLK_IRQ_MASK, ENABLED_GCU_IRQS, 0);
gcu_addr          278 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c 	malidp_write32_mask(d71->gcu_addr, BLK_CONTROL, 0x7, opmode);
gcu_addr          280 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c 	ret = dp_wait_cond(((malidp_read32(d71->gcu_addr, BLK_CONTROL) & 0x7) == opmode),
gcu_addr          293 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c 	malidp_write32(d71->gcu_addr, reg_offset, GCU_CONFIG_CVAL);
gcu_addr          298 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c 	u32 __iomem *gcu = d71->gcu_addr;
gcu_addr          353 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c 	d71->gcu_addr = mdev->reg_base;
gcu_addr          363 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c 	value = malidp_read32(d71->gcu_addr, GLB_CORE_INFO);
gcu_addr          519 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c 	u32 __iomem *reg = d71->gcu_addr;
gcu_addr          546 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c 	u32 __iomem *reg = d71->gcu_addr;
gcu_addr           36 drivers/gpu/drm/arm/display/komeda/d71/d71_dev.h 	u32 __iomem	*gcu_addr;