gcp 205 arch/arm/mach-sa1100/neponset.c static int neponset_init_gpio(struct gpio_chip **gcp, gcp 216 arch/arm/mach-sa1100/neponset.c *gcp = gc; gcp 12118 drivers/gpu/drm/i915/display/intel_display.c DRM_DEBUG_KMS("GCP: 0x%x\n", pipe_config->infoframes.gcp); gcp 12839 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(infoframes.gcp); gcp 952 drivers/gpu/drm/i915/display/intel_display_types.h u32 gcp; gcp 967 drivers/gpu/drm/i915/display/intel_hdmi.c I915_WRITE(reg, crtc_state->infoframes.gcp); gcp 992 drivers/gpu/drm/i915/display/intel_hdmi.c crtc_state->infoframes.gcp = I915_READ(reg); gcp 1009 drivers/gpu/drm/i915/display/intel_hdmi.c crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; gcp 1014 drivers/gpu/drm/i915/display/intel_hdmi.c crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;