gcfgc             138 drivers/gpu/drm/i915/display/intel_cdclk.c 	u16 gcfgc = 0;
gcfgc             140 drivers/gpu/drm/i915/display/intel_cdclk.c 	pci_read_config_word(pdev, GCFGC, &gcfgc);
gcfgc             142 drivers/gpu/drm/i915/display/intel_cdclk.c 	if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
gcfgc             147 drivers/gpu/drm/i915/display/intel_cdclk.c 	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
gcfgc             162 drivers/gpu/drm/i915/display/intel_cdclk.c 	u16 gcfgc = 0;
gcfgc             164 drivers/gpu/drm/i915/display/intel_cdclk.c 	pci_read_config_word(pdev, GCFGC, &gcfgc);
gcfgc             166 drivers/gpu/drm/i915/display/intel_cdclk.c 	if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
gcfgc             171 drivers/gpu/drm/i915/display/intel_cdclk.c 	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
gcfgc             303 drivers/gpu/drm/i915/display/intel_cdclk.c 	u16 gcfgc = 0;
gcfgc             305 drivers/gpu/drm/i915/display/intel_cdclk.c 	pci_read_config_word(pdev, GCFGC, &gcfgc);
gcfgc             307 drivers/gpu/drm/i915/display/intel_cdclk.c 	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
gcfgc             321 drivers/gpu/drm/i915/display/intel_cdclk.c 		DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);