gate_reg          191 drivers/clk/mediatek/clk-mtk.c 		gate->reg = base + mc->gate_reg;
gate_reg           67 drivers/clk/mediatek/clk-mtk.h 	uint32_t gate_reg;
gate_reg           88 drivers/clk/mediatek/clk-mtk.h 		.gate_reg = _reg,					\
gate_reg          139 drivers/clk/mediatek/clk-mtk.h 		.gate_reg = _gate_reg,					\
gate_reg           71 drivers/clk/socfpga/clk-gate-s10.c 			      void __iomem *regbase, unsigned long gate_reg,
gate_reg           85 drivers/clk/socfpga/clk-gate-s10.c 	socfpga_clk->hw.reg = regbase + gate_reg;
gate_reg          232 drivers/clk/socfpga/clk-s10.c 					clks[i].gate_reg,
gate_reg           53 drivers/clk/socfpga/stratix10-clk.h 	unsigned long		gate_reg;
gate_reg          153 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c 	unsigned int gate_reg;
gate_reg          163 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c 		gate_reg = HIBMC_MODE0_GATE;
gate_reg          167 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c 		gate_reg = HIBMC_MODE1_GATE;
gate_reg          171 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c 		gate_reg = HIBMC_MODE0_GATE;
gate_reg          174 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c 	writel(gate, mmio + gate_reg);