gam_regs 117 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct color_matrices_reg gam_regs; gam_regs 138 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; gam_regs 139 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; gam_regs 140 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; gam_regs 141 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; gam_regs 145 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12); gam_regs 146 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34); gam_regs 151 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c &gam_regs); gam_regs 155 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12); gam_regs 156 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34); gam_regs 161 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c &gam_regs); gam_regs 165 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12); gam_regs 166 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34); gam_regs 171 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c &gam_regs); gam_regs 210 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct color_matrices_reg gam_regs; gam_regs 233 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11; gam_regs 234 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11; gam_regs 235 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12; gam_regs 236 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12; gam_regs 240 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c11_c12 = REG(CM_OCSC_C11_C12); gam_regs 241 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c33_c34 = REG(CM_OCSC_C33_C34); gam_regs 245 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12); gam_regs 246 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34); gam_regs 253 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c &gam_regs); gam_regs 387 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct xfer_func_reg gam_regs; gam_regs 389 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp1_cm_get_reg_field(dpp, &gam_regs); gam_regs 391 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_b = REG(CM_RGAM_RAMA_START_CNTL_B); gam_regs 392 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_g = REG(CM_RGAM_RAMA_START_CNTL_G); gam_regs 393 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_r = REG(CM_RGAM_RAMA_START_CNTL_R); gam_regs 394 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_slope_cntl_b = REG(CM_RGAM_RAMA_SLOPE_CNTL_B); gam_regs 395 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_slope_cntl_g = REG(CM_RGAM_RAMA_SLOPE_CNTL_G); gam_regs 396 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_slope_cntl_r = REG(CM_RGAM_RAMA_SLOPE_CNTL_R); gam_regs 397 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl1_b = REG(CM_RGAM_RAMA_END_CNTL1_B); gam_regs 398 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_b = REG(CM_RGAM_RAMA_END_CNTL2_B); gam_regs 399 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl1_g = REG(CM_RGAM_RAMA_END_CNTL1_G); gam_regs 400 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_g = REG(CM_RGAM_RAMA_END_CNTL2_G); gam_regs 401 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl1_r = REG(CM_RGAM_RAMA_END_CNTL1_R); gam_regs 402 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_r = REG(CM_RGAM_RAMA_END_CNTL2_R); gam_regs 403 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.region_start = REG(CM_RGAM_RAMA_REGION_0_1); gam_regs 404 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.region_end = REG(CM_RGAM_RAMA_REGION_32_33); gam_regs 406 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs); gam_regs 416 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct xfer_func_reg gam_regs; gam_regs 418 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp1_cm_get_reg_field(dpp, &gam_regs); gam_regs 420 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_b = REG(CM_RGAM_RAMB_START_CNTL_B); gam_regs 421 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_g = REG(CM_RGAM_RAMB_START_CNTL_G); gam_regs 422 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_r = REG(CM_RGAM_RAMB_START_CNTL_R); gam_regs 423 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_slope_cntl_b = REG(CM_RGAM_RAMB_SLOPE_CNTL_B); gam_regs 424 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_slope_cntl_g = REG(CM_RGAM_RAMB_SLOPE_CNTL_G); gam_regs 425 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_slope_cntl_r = REG(CM_RGAM_RAMB_SLOPE_CNTL_R); gam_regs 426 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl1_b = REG(CM_RGAM_RAMB_END_CNTL1_B); gam_regs 427 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_b = REG(CM_RGAM_RAMB_END_CNTL2_B); gam_regs 428 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl1_g = REG(CM_RGAM_RAMB_END_CNTL1_G); gam_regs 429 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_g = REG(CM_RGAM_RAMB_END_CNTL2_G); gam_regs 430 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl1_r = REG(CM_RGAM_RAMB_END_CNTL1_R); gam_regs 431 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_r = REG(CM_RGAM_RAMB_END_CNTL2_R); gam_regs 432 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.region_start = REG(CM_RGAM_RAMB_REGION_0_1); gam_regs 433 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.region_end = REG(CM_RGAM_RAMB_REGION_32_33); gam_regs 435 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs); gam_regs 450 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct color_matrices_reg gam_regs; gam_regs 487 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11; gam_regs 488 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11; gam_regs 489 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12; gam_regs 490 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12; gam_regs 494 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c11_c12 = REG(CM_ICSC_C11_C12); gam_regs 495 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c33_c34 = REG(CM_ICSC_C33_C34); gam_regs 499 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12); gam_regs 500 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34); gam_regs 507 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c &gam_regs); gam_regs 540 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct xfer_func_reg gam_regs; gam_regs 542 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp1_cm_get_degamma_reg_field(dpp, &gam_regs); gam_regs 544 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_b = REG(CM_DGAM_RAMB_START_CNTL_B); gam_regs 545 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_g = REG(CM_DGAM_RAMB_START_CNTL_G); gam_regs 546 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_r = REG(CM_DGAM_RAMB_START_CNTL_R); gam_regs 547 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_slope_cntl_b = REG(CM_DGAM_RAMB_SLOPE_CNTL_B); gam_regs 548 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_slope_cntl_g = REG(CM_DGAM_RAMB_SLOPE_CNTL_G); gam_regs 549 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_slope_cntl_r = REG(CM_DGAM_RAMB_SLOPE_CNTL_R); gam_regs 550 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl1_b = REG(CM_DGAM_RAMB_END_CNTL1_B); gam_regs 551 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_b = REG(CM_DGAM_RAMB_END_CNTL2_B); gam_regs 552 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl1_g = REG(CM_DGAM_RAMB_END_CNTL1_G); gam_regs 553 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_g = REG(CM_DGAM_RAMB_END_CNTL2_G); gam_regs 554 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl1_r = REG(CM_DGAM_RAMB_END_CNTL1_R); gam_regs 555 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_r = REG(CM_DGAM_RAMB_END_CNTL2_R); gam_regs 556 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.region_start = REG(CM_DGAM_RAMB_REGION_0_1); gam_regs 557 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.region_end = REG(CM_DGAM_RAMB_REGION_14_15); gam_regs 560 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs); gam_regs 569 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c struct xfer_func_reg gam_regs; gam_regs 571 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c dpp1_cm_get_degamma_reg_field(dpp, &gam_regs); gam_regs 573 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_b = REG(CM_DGAM_RAMA_START_CNTL_B); gam_regs 574 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_g = REG(CM_DGAM_RAMA_START_CNTL_G); gam_regs 575 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_cntl_r = REG(CM_DGAM_RAMA_START_CNTL_R); gam_regs 576 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_slope_cntl_b = REG(CM_DGAM_RAMA_SLOPE_CNTL_B); gam_regs 577 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_slope_cntl_g = REG(CM_DGAM_RAMA_SLOPE_CNTL_G); gam_regs 578 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_slope_cntl_r = REG(CM_DGAM_RAMA_SLOPE_CNTL_R); gam_regs 579 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl1_b = REG(CM_DGAM_RAMA_END_CNTL1_B); gam_regs 580 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_b = REG(CM_DGAM_RAMA_END_CNTL2_B); gam_regs 581 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl1_g = REG(CM_DGAM_RAMA_END_CNTL1_G); gam_regs 582 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_g = REG(CM_DGAM_RAMA_END_CNTL2_G); gam_regs 583 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl1_r = REG(CM_DGAM_RAMA_END_CNTL1_R); gam_regs 584 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.start_end_cntl2_r = REG(CM_DGAM_RAMA_END_CNTL2_R); gam_regs 585 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.region_start = REG(CM_DGAM_RAMA_REGION_0_1); gam_regs 586 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.region_end = REG(CM_DGAM_RAMA_REGION_14_15); gam_regs 588 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs); gam_regs 239 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct xfer_func_reg gam_regs; gam_regs 241 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dcn20_dpp_cm_get_reg_field(dpp, &gam_regs); gam_regs 243 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMA_START_CNTL_B); gam_regs 244 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMA_START_CNTL_G); gam_regs 245 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMA_START_CNTL_R); gam_regs 246 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMA_SLOPE_CNTL_B); gam_regs 247 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMA_SLOPE_CNTL_G); gam_regs 248 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMA_SLOPE_CNTL_R); gam_regs 249 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMA_END_CNTL1_B); gam_regs 250 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMA_END_CNTL2_B); gam_regs 251 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMA_END_CNTL1_G); gam_regs 252 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMA_END_CNTL2_G); gam_regs 253 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMA_END_CNTL1_R); gam_regs 254 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMA_END_CNTL2_R); gam_regs 255 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.region_start = REG(CM_BLNDGAM_RAMA_REGION_0_1); gam_regs 256 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.region_end = REG(CM_BLNDGAM_RAMA_REGION_32_33); gam_regs 258 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs); gam_regs 267 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c struct xfer_func_reg gam_regs; gam_regs 269 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c dcn20_dpp_cm_get_reg_field(dpp, &gam_regs); gam_regs 271 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_cntl_b = REG(CM_BLNDGAM_RAMB_START_CNTL_B); gam_regs 272 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_cntl_g = REG(CM_BLNDGAM_RAMB_START_CNTL_G); gam_regs 273 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_cntl_r = REG(CM_BLNDGAM_RAMB_START_CNTL_R); gam_regs 274 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_slope_cntl_b = REG(CM_BLNDGAM_RAMB_SLOPE_CNTL_B); gam_regs 275 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_slope_cntl_g = REG(CM_BLNDGAM_RAMB_SLOPE_CNTL_G); gam_regs 276 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_slope_cntl_r = REG(CM_BLNDGAM_RAMB_SLOPE_CNTL_R); gam_regs 277 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl1_b = REG(CM_BLNDGAM_RAMB_END_CNTL1_B); gam_regs 278 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl2_b = REG(CM_BLNDGAM_RAMB_END_CNTL2_B); gam_regs 279 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl1_g = REG(CM_BLNDGAM_RAMB_END_CNTL1_G); gam_regs 280 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl2_g = REG(CM_BLNDGAM_RAMB_END_CNTL2_G); gam_regs 281 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl1_r = REG(CM_BLNDGAM_RAMB_END_CNTL1_R); gam_regs 282 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.start_end_cntl2_r = REG(CM_BLNDGAM_RAMB_END_CNTL2_R); gam_regs 283 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.region_start = REG(CM_BLNDGAM_RAMB_REGION_0_1); gam_regs 284 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c gam_regs.region_end = REG(CM_BLNDGAM_RAMB_REGION_32_33); gam_regs 286 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs); gam_regs 290 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c struct xfer_func_reg gam_regs; gam_regs 292 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc2_ogam_get_reg_field(mpc, &gam_regs); gam_regs 294 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMB_START_CNTL_B[mpcc_id]); gam_regs 295 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMB_START_CNTL_G[mpcc_id]); gam_regs 296 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMB_START_CNTL_R[mpcc_id]); gam_regs 297 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_B[mpcc_id]); gam_regs 298 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_G[mpcc_id]); gam_regs 299 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMB_SLOPE_CNTL_R[mpcc_id]); gam_regs 300 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMB_END_CNTL1_B[mpcc_id]); gam_regs 301 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl2_b = REG(MPCC_OGAM_RAMB_END_CNTL2_B[mpcc_id]); gam_regs 302 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl1_g = REG(MPCC_OGAM_RAMB_END_CNTL1_G[mpcc_id]); gam_regs 303 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl2_g = REG(MPCC_OGAM_RAMB_END_CNTL2_G[mpcc_id]); gam_regs 304 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl1_r = REG(MPCC_OGAM_RAMB_END_CNTL1_R[mpcc_id]); gam_regs 305 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl2_r = REG(MPCC_OGAM_RAMB_END_CNTL2_R[mpcc_id]); gam_regs 306 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.region_start = REG(MPCC_OGAM_RAMB_REGION_0_1[mpcc_id]); gam_regs 307 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.region_end = REG(MPCC_OGAM_RAMB_REGION_32_33[mpcc_id]); gam_regs 309 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c cm_helper_program_xfer_func(mpc20->base.ctx, params, &gam_regs); gam_regs 317 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c struct xfer_func_reg gam_regs; gam_regs 319 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c mpc2_ogam_get_reg_field(mpc, &gam_regs); gam_regs 321 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_cntl_b = REG(MPCC_OGAM_RAMA_START_CNTL_B[mpcc_id]); gam_regs 322 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_cntl_g = REG(MPCC_OGAM_RAMA_START_CNTL_G[mpcc_id]); gam_regs 323 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_cntl_r = REG(MPCC_OGAM_RAMA_START_CNTL_R[mpcc_id]); gam_regs 324 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_slope_cntl_b = REG(MPCC_OGAM_RAMA_SLOPE_CNTL_B[mpcc_id]); gam_regs 325 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_slope_cntl_g = REG(MPCC_OGAM_RAMA_SLOPE_CNTL_G[mpcc_id]); gam_regs 326 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_slope_cntl_r = REG(MPCC_OGAM_RAMA_SLOPE_CNTL_R[mpcc_id]); gam_regs 327 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl1_b = REG(MPCC_OGAM_RAMA_END_CNTL1_B[mpcc_id]); gam_regs 328 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl2_b = REG(MPCC_OGAM_RAMA_END_CNTL2_B[mpcc_id]); gam_regs 329 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl1_g = REG(MPCC_OGAM_RAMA_END_CNTL1_G[mpcc_id]); gam_regs 330 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl2_g = REG(MPCC_OGAM_RAMA_END_CNTL2_G[mpcc_id]); gam_regs 331 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl1_r = REG(MPCC_OGAM_RAMA_END_CNTL1_R[mpcc_id]); gam_regs 332 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.start_end_cntl2_r = REG(MPCC_OGAM_RAMA_END_CNTL2_R[mpcc_id]); gam_regs 333 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.region_start = REG(MPCC_OGAM_RAMA_REGION_0_1[mpcc_id]); gam_regs 334 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c gam_regs.region_end = REG(MPCC_OGAM_RAMA_REGION_32_33[mpcc_id]); gam_regs 336 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c cm_helper_program_xfer_func(mpc20->base.ctx, params, &gam_regs);