g4x               725 drivers/gpu/drm/i915/display/intel_display_types.h 		} g4x;
g4x              1015 drivers/gpu/drm/i915/display/intel_display_types.h 			struct g4x_wm_state g4x;
g4x              1601 drivers/gpu/drm/i915/i915_drv.h 			struct g4x_wm_values g4x;
g4x               468 drivers/gpu/drm/i915/intel_pm.c 		dev_priv->wm.g4x.cxsr = enable;
g4x              1182 drivers/gpu/drm/i915/intel_pm.c 		struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
g4x              1201 drivers/gpu/drm/i915/intel_pm.c 		struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
g4x              1231 drivers/gpu/drm/i915/intel_pm.c 		struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
g4x              1272 drivers/gpu/drm/i915/intel_pm.c 			      crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],
g4x              1273 drivers/gpu/drm/i915/intel_pm.c 			      crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],
g4x              1274 drivers/gpu/drm/i915/intel_pm.c 			      crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);
g4x              1278 drivers/gpu/drm/i915/intel_pm.c 				      crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc,
g4x              1279 drivers/gpu/drm/i915/intel_pm.c 				      crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);
g4x              1288 drivers/gpu/drm/i915/intel_pm.c 	const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
g4x              1337 drivers/gpu/drm/i915/intel_pm.c 	struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
g4x              1366 drivers/gpu/drm/i915/intel_pm.c 	raw = &crtc_state->wm.g4x.raw[level];
g4x              1375 drivers/gpu/drm/i915/intel_pm.c 	raw = &crtc_state->wm.g4x.raw[level];
g4x              1387 drivers/gpu/drm/i915/intel_pm.c 	raw = &crtc_state->wm.g4x.raw[level];
g4x              1424 drivers/gpu/drm/i915/intel_pm.c 	struct g4x_wm_state *intermediate = &new_crtc_state->wm.g4x.intermediate;
g4x              1425 drivers/gpu/drm/i915/intel_pm.c 	const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal;
g4x              1430 drivers/gpu/drm/i915/intel_pm.c 	const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;
g4x              1508 drivers/gpu/drm/i915/intel_pm.c 		const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
g4x              1530 drivers/gpu/drm/i915/intel_pm.c 		const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
g4x              1543 drivers/gpu/drm/i915/intel_pm.c 	struct g4x_wm_values *old_wm = &dev_priv->wm.g4x;
g4x              1569 drivers/gpu/drm/i915/intel_pm.c 	crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
g4x              1584 drivers/gpu/drm/i915/intel_pm.c 	crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
g4x              5988 drivers/gpu/drm/i915/intel_pm.c 	struct g4x_wm_values *wm = &dev_priv->wm.g4x;
g4x              5998 drivers/gpu/drm/i915/intel_pm.c 		struct g4x_wm_state *active = &crtc->wm.active.g4x;
g4x              6024 drivers/gpu/drm/i915/intel_pm.c 		raw = &crtc_state->wm.g4x.raw[level];
g4x              6031 drivers/gpu/drm/i915/intel_pm.c 		raw = &crtc_state->wm.g4x.raw[level];
g4x              6040 drivers/gpu/drm/i915/intel_pm.c 		raw = &crtc_state->wm.g4x.raw[level];
g4x              6052 drivers/gpu/drm/i915/intel_pm.c 		crtc_state->wm.g4x.optimal = *active;
g4x              6053 drivers/gpu/drm/i915/intel_pm.c 		crtc_state->wm.g4x.intermediate = *active;
g4x              6084 drivers/gpu/drm/i915/intel_pm.c 		struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
g4x              6093 drivers/gpu/drm/i915/intel_pm.c 				&crtc_state->wm.g4x.raw[level];
g4x              6102 drivers/gpu/drm/i915/intel_pm.c 					&crtc_state->wm.g4x.raw[level];
g4x              6116 drivers/gpu/drm/i915/intel_pm.c 		crtc_state->wm.g4x.intermediate =
g4x              6117 drivers/gpu/drm/i915/intel_pm.c 			crtc_state->wm.g4x.optimal;
g4x              6118 drivers/gpu/drm/i915/intel_pm.c 		crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;