fxn                36 arch/x86/events/amd/iommu.h 				u8 fxn, u64 *value);
fxn                39 arch/x86/events/amd/iommu.h 				u8 fxn, u64 *value);
fxn              1659 drivers/iommu/amd_iommu_init.c 				u8 fxn, u64 *value, bool is_write);
fxn              3133 drivers/iommu/amd_iommu_init.c 				u8 fxn, u64 *value, bool is_write)
fxn              3143 drivers/iommu/amd_iommu_init.c 	if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7)))
fxn              3146 drivers/iommu/amd_iommu_init.c 	offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn);
fxn              3170 drivers/iommu/amd_iommu_init.c int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
fxn              3175 drivers/iommu/amd_iommu_init.c 	return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false);
fxn              3179 drivers/iommu/amd_iommu_init.c int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
fxn              3184 drivers/iommu/amd_iommu_init.c 	return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true);
fxn              1485 fs/gfs2/quota.c 			       int (*fxn)(struct super_block *sb, int type),
fxn              1490 fs/gfs2/quota.c 		int error = fxn(sdp->sd_vfs, 0);