fw_offset         579 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c 	uint64_t fw_offset = 0;
fw_offset         602 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c 			amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset,
fw_offset         603 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c 						    adev->firmware.fw_buf_ptr + fw_offset);
fw_offset         608 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c 				amdgpu_ucode_patch_jt(ucode,  adev->firmware.fw_buf_mc + fw_offset,
fw_offset         609 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c 						    adev->firmware.fw_buf_ptr + fw_offset);
fw_offset         610 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c 				fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
fw_offset         612 drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c 			fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE);
fw_offset        1080 drivers/input/touchscreen/melfas_mip4.c 			 const u8 *fw_data, u32 fw_size, u32 fw_offset)
fw_offset        1108 drivers/input/touchscreen/melfas_mip4.c 	for (offset = fw_offset;
fw_offset        1109 drivers/input/touchscreen/melfas_mip4.c 	     offset < fw_offset + fw_size;
fw_offset        1871 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c 	u16 fw_offset, fw_ptp_cfg_offset;
fw_offset        1881 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c 	if (hw->eeprom.ops.read(hw, offset, &fw_offset))
fw_offset        1884 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c 	if (fw_offset == 0 || fw_offset == 0xFFFF)
fw_offset        1888 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c 	offset = fw_offset + IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR;
fw_offset        1919 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c 	u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
fw_offset        1923 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c 	status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
fw_offset        1925 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c 	if (status || fw_offset == 0 || fw_offset == 0xFFFF)
fw_offset        1929 drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c 	status = hw->eeprom.ops.read(hw, (fw_offset +
fw_offset         397 sound/soc/intel/haswell/sst-haswell-ipc.h 	u32 fw_offset);